View ST92T141K4B6_3099425.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

october 2001 1/179 rev. 1.7 st92141 8/16-bit mcu for 3-phase ac motor control n register file based 8/16 bit core architecture with run, wfi, slow, halt and stop modes n 0-25 mhz operation (internal clock) @ 5v10% voltage range n -40c to +85c operating temperature range n fully programmable pll clock generator, with frequency multiplication and low frequency, low cost external crystal (3-5 mhz) n minimum instruction cycle time: 160 ns - (@ 25 mhz internal clock frequency) n internal memory: C eprom/otp/fastrom 16k bytes C ram 512 bytes n 224 general purpose registers available as ram, accumulators or index pointers (register file) n 32-pin dual inline and 34-pin small outline packages n 15 programmable i/o pins with schmitt trigger input, including 4 high sink outputs (20ma @ v ol =3v) n 4 wake-up interrupts (one usable as non- maskable interrupt) for emergency event management n 3-phase induction motor controller (imc) peripheral with 3 pairs of pwm outputs and asynchronous emergency stop n serial peripheral interface (spi) with master/ slave mode capability n 16-bit timer with 8-bit prescaler usable as a watchdog timer n 16-bit standard timer with 8-bit prescaler n 16-bit extended function timer with prescaler, 2 input captures and 2 output compares n 8-bit analog to digital converter allowing up to 6 input channels with autoscan and watchdog capability n low voltage detector reset n rich instruction set with 14 addressing modes n division-by-zero trap generation n versatile development tools, including assembler, linker, c-compiler, archiver, source level debugger and hardware emulators with real-time operating system available from third parties device summary device program memory (bytes) ram (bytes) package st92p141 16k fastrom 512 psdip32/ so34 st92e141 16k eprom 512 csdip32w st92t141 16k otp 512 psdip32/ so34 psdip32 so34 shrink csdip32w 9
2/179 table of contents 179 1 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 st9+ core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3 system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.5 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.6 3-phase induction motor controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.7 watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.8 standard timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.9 extended function timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.10 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.11 analog/digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.1 i/o port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 i/o port reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3.1 memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3.2 eprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.1 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.2 register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.1 central interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.2 flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 2.3.3 register pointing techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.4 paged registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.5 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.6 stack pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 2.4 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5 memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6 address space extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.1 addressing 16-kbyte pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.2 addressing 64-kbyte segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7 mmu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7.1 dpr[3:0]: data page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7.2 csr: code segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7.3 isr: interrupt segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.7.4 dmasr: dma segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8 mmu usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.1 normal program execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.3 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3/179 table of contents 3.2 interrupt vectoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.1 divide by zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.2 segment paging during interrupt routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3 interrupt priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4 priority level arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.1 priority level 7 (lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.2 maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.3 simultaneous interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.4 dynamic priority level modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5 arbitration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.1 concurrent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.2 nested mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.7 top level interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.8 on-chip peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.9 nmi/wkp0 line management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.9.1 nmi/wake-up event handling in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.9.2 nmi/wake-up event handling in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.9.3 unused wake up management unit lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.10 interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.11 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.12 wake-up / interrupt lines management unit (wuimu) . . . . . . . . . . . . . . . . . . 55 3.12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.12.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 3.12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.12.4 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.12.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4 em configuration registers (em) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 reset and clock control unit (rccu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.1 clock control unit overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.1 pll clock multiplier programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.2 cpu clock prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.3 peripheral clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.5 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4 clock control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.6 reset/stop manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.6.1 reset pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.7 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.8 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 specific port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4/179 table of contents 179 6.3 port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4 input/output bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.5 alternate function architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.1 pin declared as i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.2 pin declared as an alternate function input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.5.3 pin declared as an alternate function output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.6 i/o status after wfi, halt and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1 timer/watchdog (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.1.3 watchdog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.1.4 wdt interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.1.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.2 standard timer (stim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2.3 interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.2.4 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.2.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.3 extended function timer (eft) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.3.4 interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.3.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.4 3-phase induction motor controller (imc) . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 16 7.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.4.4 tacho counter operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4.5 imc operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4.6 imc output selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.4.7 nmi management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 35 7.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.5.5 interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.5.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.6 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 47 7.6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7.6.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7.6.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5/179 table of contents 9 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 74 9.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 9.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 9.3 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 10 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6/179 st92141 - general description 1 general description 1.1 introduction the st92141 microcontroller is developed and manufactured by stmicroelectronics using a pro- prietary n-well hcmos process. its performance derives from the use of a flexible 256-register pro- gramming model for ultra-fast context switching and real-time event response. the intelligent on- chip peripherals offload the st9 core from i/o and data management processing tasks allowing criti- cal application tasks to get the maximum use of core resources. the new-generation st9 mcu devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 st9+ core the advanced core consists of the central processing unit (cpu), the register file, the inter- rupt controller, and the memory management unit. the mmu allows addressing of up to 4 megabytes of program and data mapped into a single linear space. four independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit inter- rupt bus which connects the interrupt controllers in the on-chip peripherals with the core. note: the dma features of the st9+ core are not used by the on-chip peripherals of the st92141. this multiple bus architecture makes the st9 fam- ily devices highly efficient for accessing on and off- chip memory and fast exchange of data with the on-chip peripherals. the general-purpose registers can be used as ac- cumulators, index registers, or address pointers. adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. although the st9 has an 8-bit alu, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. 1.1.2 power saving modes to optimize performance versus power consump- tion, a range of operating modes can be dynami- cally selected by software according to the re- quirements of the application. run mode. this is the full speed execution mode with cpu and peripherals running at the maximum clock speed delivered either by the phase locked loop controlled by the rccu (reset and clock control unit), directly by the oscillator or by an ex- ternal source (dedicated pin or alternate func- tion). slow mode . power consumption can be signifi- cantly reduced by running the cpu and the periph- erals at reduced clock speed using the cpu pres- caler and rccu clock divider. wait for interrupt mode. the wait for interrupt (wfi) instruction suspends program execution un- til an interrupt request is acknowledged. during wfi, the cpu clock is halted while the peripheral with interrupt capability and interrupt controller are kept running at a frequency that can be pro- grammed by software in the rccu registers. in this mode, the power consumption of the device can be reduced by more than 95% (low power wfi). halt mode. when executing the halt instruction, and if the watchdog is not enabled, the cpu and its peripherals stop operating. if however the watchdog is enabled, the halt instruction has no effect. the main difference between halt mode and stop mode is that a reset is necessary to exit from halt mode which causes the system to be reinitialized. stop mode. when stop mode is requested by ex- ecuting the stop sequence (see wake-up man- agement unit section), the cpu and the peripher- als stop operating. operations resume after a wake-up line is activated. the difference between stop mode and halt mode is in the way the cpu exits each state: when the stop sequence is ex- ecuted, the status of the registers is recorded, and when the system exits from stop mode the cpu continues execution with the same status, without a system reset. the watchdog counter, if enabled, is stopped. af- ter exiting stop mode it restarts counting from where it left off. when the mcu exits from stop mode, the oscil- lator, which was also sleeping, requires a start-up time to restart working properly. an internal coun- ter is present to guarantee that, after exiting stop mode, all operations take place with the clock sta- bilised. 1.1.3 system clock a programmable pll clock generator allows standard 3 to 5 mhz crystals to be used to obtain a large range of internal frequencies up to 25mhz. 9
7/179 st92141 - general description 1.1.4 low voltage reset the on-chip low voltage detector (lvd) gener- ates a static reset when the supply voltage is be- low a reference value. the lvd works both during power-on as well as when the power supply drops (brown-out). the reference value for the voltage drop is lower than the reference value for power- on in order to avoid a parasitic reset when the mcu starts running and sinks current on the sup- ply (hysteresis). 1.1.5 i/o ports the i/o lines are grouped into two i/o ports and can be configured on a bit basis to provide timing, status signals, an address/data bus for timer in- puts and outputs, analog inputs, external wake-up lines and serial or parallel i/o. 1.1.6 3-phase induction motor controller the imc controller is designed for variable speed motor control applications. three pairs of pwm outputs are available for controlling a three-phase motor drive. rotor speed feedback is provided by capturing a tachogenerator input signal. emergen- cy stop is provided by putting the pwm outputs in high impedance mode upon asynchronous faulty event on nmi pin. 1.1.7 watchdog timer (wdt) the watchdog timer can be used to monitor sys- tem integrity. when enabled, it generates a reset after a timeout period unless the counter is re- freshed by the application software. for additional security, watchdog function can be enabled by hardware using a specific pin. 1.1.8 standard timer the standard timer includes a programmable 16- bit down-counter and an associated 8-bit prescaler with single and continuous counting modes. 1.1.9 extended function timer the extended function timer can be used for a wide range of standard timing tasks. it has a 16-bit free running counter with programmable prescal- er. each timer can have up to 2 input capture and 2 output compare pins with associated registers. this allows applications to measure pulse inter- vals or generate pulse waveforms. timer overflow and other events are flagged in a status register with optional interrupt generation. 1.1.10 serial peripheral interface (spi) the spi bus is used to communicate with external devices via the spi, or i2c bus communication standards. 1.1.11 analog/digital converter (adc) the adc provides up to 6 analog inputs with on- chip sample and hold. the analog watchdog gen- erates an interrupt when the input voltage moves out of a preset threshold. 9
8/179 st92141 - general description figure 1. st92141 block diagram register file 256 bytes st9+ core 8/16-bit cpu interrupt management memory bus rccu + lvd register bus watchdog miso mosi sck ssn ef timer spi imc tacho uh ul vh vl wh wl stin stout all alternate functions ( italic characters ) are mapped on port3 and port5 fully prog. i/os p3[6:0] p5[7:0] nmi wkup[3:0] int0 int6 oscin oscout reset intclk ck_af ram 512 bytes eprom/ fastrom 16k a/d converter with analog watchdog ain[7:2] extrg wdin wdout stim timer icap1 ocmp1 icap2 ocmp2 extclk 9
9/179 st92141 - general description 1.2 pin description st92e141 134 18 17 v ss tacho vh vl wh wl uh ul n.c. v pp p5.0/wkup1/icap2 p5.1/nmi/wkup0 reset oscout oscin v ss v dd psdip32/csdip32w package so34 package st92e141 132 17 16 v ss tacho vh vl wh wl uh ul v pp p5.0/wkup1/icap2 p5.1/nmi/wkup0 reset oscout oscin v ss v dd v dd mosi/p3.0 miso/p3.1 sck/stin/wkup3/p3.2 stout/ssn/p3.3 extrg/ocmp2/p3.4 int6/ocmp1/p3.5 icap1/wkup2/p3.6 av dd av ss intclk/ain7/p5.7 ck_af/ain6/p5.6 ain5/p5.5 ain4/p5.4 ain3/extclk/wdout/p5.3 ain2/int0/wdin/p5.2 v dd mosi/p3.0 miso/p3.1 sck/stin/wkup3/p3.2 stout/ssn/p3.3 extrg/ocmp2/p3.4 int6/ocmp1/p3.5 icap1/wkup2/p3.6 n.c. av dd av ss intclk/ain7/p5.7 ck_af/ain6/p5.6 ain5/p5.5 ain4/p5.4 ain3/extclk/wdout/p5.3 ain2/int0/wdin/p5.2 9
10/179 st92141 - general description 9 table 1. power supply pins table 2. primary function pins name function sdip32 so34 v pp programming voltage for eprom/otp devices. must be connected to v ss in user mode. 24 25 v dd main power supply voltage (5v 10% (2 pins internally connected) 17 18 11 v ss digital circuit ground (2 pins in- ternally connected) 18 19 32 34 av dd analog v dd of the analog to digit- al converter 910 av ss analog v ss of the analog to digit- al converter 10 11 name function sdip32 so34 tacho signal input from a tachogenera- tor to the imc controller for measuring the rotor speed 31 33 uh u-phase pwm output signal 26 28 vh v-phase pwm output signal 30 32 wh w-phase pwm output signal 28 30 ul the complemented uh, vh, wh output signals with added dead time to avoid crossover conduc- tion from the power driver 25 27 vl 29 31 wl 27 29 reset reset (input, active low). the st9+ is initialised by the reset signal. with the deactivation of reset , program execution be- gins from the memory location pointed to by the vector con- tained in memory locations 00h and 01h 21 22 oscin oscin is the input of the oscilla- tor inverter and internal clock generator. oscin and oscout connect a parallel-resonant crys- tal (3 to 5 mhz), or an external source to the on-chip clock oscil- lator and buffer 19 20 oscout oscout is the output of the os- cillator inverter 20 21
11/179 st92141 - general description 1.2.1 i/o port configuration all ports can be individually configured as input, bi- directional, output, or alternate function. refer to the port bit configuration table in the i/o port chapter. all i/os are implemented with a high hysteresis or standard hysteresis schmitt trigger function (see electrical characteristics). weak pull-up = this column indicates if a weak pull-up is present or not (refer to table 3). C if wpu = yes, then the wpu can be enabled/dis- able by software C if wpu = no, then enabling the wpu by software has no effect all port output configurations can be software se- lected on a bit basis to provide push-pull or open drain driving capabilities. for all ports, when con- figured as open-drain, the voltage on the pin must never exceed the v dd power line value (refer to electrical characteristics section). 1.2.2 i/o port reset state i/os are reset asynchronously as soon as the re- set pin is asserted low. all i/os are forced by the reset in "floating input" configuration mode. warning when a common pin is declared to be connected to an alternate function input and to an alternate function output, the user must be aware of the fact that the alternate function output signal always in- puts to the alternate function module declared as input. when any given pin is declared to be connected to a digital alternate function input, the user must be aware of the fact that the alternate function input is always connected to the pin. when a given pin is declared to be connected to an analog alternate function input (adc input for example) and if this pin is programmed in the "af-od" mode, the digit- al input path is disconnected from the pin to pre- vent any dc consumption. table 3. i/o port characteristics legend: od = open drain; hc= high current input output weak pull-up reset state port 3[4:0] port 3[6:5] schmitt trigger (high hysteresis) schmitt trigger (high hysteresis) push-pull/od push-pull/od (hc) yes yes floating input floating input port 5.0 port 5.1 port 5.2 port 5[7:3] schmitt trigger (high hysteresis) schmitt trigger (high hysteresis) schmitt trigger (standard hysteresis) schmitt trigger (standard hysteresis) push-pull/od (hc) push-pull/od push-pull/od (hc) push-pull/od yes yes yes yes floating input floating input floating input floating input 9
12/179 st92141 - general description table 4. st92141 alternate functions how to configure the i/o ports to configure the i/o ports, use the information in table 3 and table 4 and the port bit configuration table in the i/o ports chapter on page 81 . i/o note = the hardware characteristics fixed for each port line in table 3 . all i/o inputs have schmitt trigger fixed by hard- ware so selecting cmos or ttl input by software has no effect, the input will always be schmitt trig- ger. in particular, the schmitt triggers present on the p5[7:2] pins have a standard hysteresis whereas the remaining pins have schmitt triggers with high hysteresis (refer to electrical specifica- tions). alternate functions (af) = more than one af cannot be assigned to an external pin at the same time: port name general purpose i/o pin no. alternate functions sdip32 pso34 p3.0 all ports useable for general pur- pose i/o (input, output or bidi- rectional) 2 2 mosi i/o spi master output/slave input data p3.1 3 3 miso i/o spi master input/slave output data p3.2 4 4 wkup3 i wake-up line 3 stin i standard timer input sck i/o spi serial clock input/output p3.3 5 5 ssn i spi slave select stout o standard timer output p3.4 6 6 extrg i a/d external trigger ocpm2 o ext. timer output compare 2 p3.5 7 7 int6 i external interrupt 6 ocmp1 o ext. timer - output compare 1 p3.6 8 8 icap1 i ext. timer - input capture 1 wkup2 i wake-up line 2 p5.0 23 24 icap2 i ext. timer - input capture 2 wkup1 i wake-up line 1 p5.1 22 23 nmi i not maskable int. wkup0 i wake-up line 0 p5.2 16 17 ain2 i analog data input 2 int0 i external interrupt 0 wdin i watchdog input p5.3 15 16 ain3 i analog data input 3 extclk i ext. timer - input clock wdout o watchdog output p5.4 14 15 ain4 i analog data input 4 p5.5 13 14 ain5 i analog data input 5 p5.6 12 13 ain6 i analog data input 6 ck_af i clock alternative source p5.7 11 12 ain7 i analog data input 7 intclk o internal main clock 9
13/179 st92141 - general description an alternate function can be selected as follows. af inputs: C af is selected implicitly by enabling the corre- sponding peripheral. exceptions to this are adc analog inputs which must be explicitly selected as af by software. af outputs or bidirectional lines: C in the case of outputs or i/os, af is selected ex- plicitly by software. example 1: standard timer input af: stin, port: p3.2, i/o note: schmitt trigger. write the port configuration bits: p3c2.2=1 p3c1.2=0 p3c0.2=1 or p3c2.2=0 p3c1.2=0 p3c0.2=1 enable the standard timer input by software as described in the stim chapter. example 2: standard timer output af: stout, port: p3.3 write the port configuration bits (for af output push-pull): p3c2.3=0 p3c1.3=1 p3c0.3=1 example 3: adc analog input af: ain2, port: p5.2, i/o note: does not apply to analog inputs write the port configuration bits: p5c2.2=1 p5c1.2=1 p5c0.2=1 9
14/179 st92141 - general description 1.3 memory map 1.3.1 memory configuration the program memory space of the st92141, 16k bytes of directly addressable on-chip memory, is fully available to the user. the first 256 memory locations from address 0 to ffh hold the reset vector, the top-level (pseudo non-maskable) interrupt, the divide by zero trap routine vector and, optionally, the interrupt vector table for use with the on-chip peripherals and the external interrupt sources. apart from this case no other part of the program memory has a predeter- mined function except segment 21h which is re- served for use by stmicroelectronics. 1.3.2 eprom programming the 16k bytes of eprom memory of the st92e141 may be programmed by using the eprom programming boards (epb) or gang pro- grammers available from stmicroelectronics. eprom erasing the eprom of the windowed package of the st92e141 may be erased by exposure to ultra-vi- olet light. the erasure characteristic of the st92e141 is such that erasure begins when the memory is ex- posed to light with a wave lengths shorter than ap- proximately 4000?. it should be noted that sunlight and some types of fluorescent lamps have wave- lengths in the range 3000-4000?. it is thus recom- mended that the window of the st92e141 packag- es be covered by an opaque label to prevent unin- tentional erasure problems when testing the appli- cation in such an environment. the recommended erasure procedure of the eprom is the exposure to short wave ultraviolet light which have a wave-length 2537?. the inte- grated dose (i.e. u.v. intensity x exposure time) for erasure should be a minimum of 15w-sec/cm2. the erasure time with this dosage is approximate- ly 30 minutes using an ultraviolet lamp with 12000mw/cm2 power rating. the st92e141 should be placed within 2.5cm (1 inch) of the lamp tubes during erasure. table 5. first 6 bytes of program space figure 2. memory map 0 address high of power on reset routine 1 address low of power on reset routine 2 address high of divide by zero trap subroutine 3 address low of divide by zero trap subroutine 4 address high of top level interrupt routine 5 address low of top level interrupt routine segment 0 64 kbytes 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 0 - 16 kbytes page 1 - 16 kbytes page 2 - 16 kbytes page 3 - 16 kbytes segment 20h 64 kbytes 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes 200000h 200200h ram 512 bytes internal reserved segment 21h 64 kbytes 20ffffh 220000h 210000h internal rom reserved reserved reserved max. 64 kbytes 000000h 004000h fastrom/eprom 16 kbytes 003fffh 9
15/179 st92141 - general description 1.4 register map the following pages contain a list of st92141 reg- isters, grouped by peripheral or function. be very careful to correctly program both: C the set of registers dedicated to a particular function or peripheral. C registers common to other functions. C in particular, double-check that any registers with undefined reset values have been correct- ly initialised. warning : note that in the eivr and each ivr register, all bits are significant. take care when defining base vector addresses that entries in the interrupt vector table do not overlap. table 6. common registers function or peripheral common registers adc cicr + nicr + i/o port registers wdt cicr + nicr + external interrupt registers + i/o port registers i/o ports i/o port registers + moder external interrupt interrupt registers + i/o port registers rccu interrupt registers + moder 9
16/179 st92141 - general description table 7. group f pages resources available on the st92141 devices: register page 0 2 3 7 11 21 28 48 51 55 57 63 r255 res. res. res. res. res. res. eft0 imc imc res. wu a/d0 r254 port 3 r253 r252 wcr r251 wdt res. r250 r249 mmu r248 res. r247 ext int res. res. r246 port 5 em rccu r245 res. r244 mmu r243 res. spi0 stim0 r242 rccu r241 res. res. r240 rccu 9
17/179 st92141 - general description table 8. detailed register map page (decimal) block reg. no. register name description reset value hex. doc. page n/a core r230 cicr central interrupt control register 87 52 r231 flagr flag register 00 24 r232 rp0 pointer 0 register xx 26 r233 rp1 pointer 1 register xx 26 r234 ppr page pointer register xx 28 r235 moder mode register e0 28 r236 usphr user stack pointer high register xx 30 r237 usplr user stack pointer low register xx 30 r238 ssphr system stack pointer high reg. xx 30 r239 ssplr system stack pointer low reg. xx 30 i/o port 5:4,2:0 r224 p0dr port 0 data register ff 79 r225 p1dr port 1 data register ff r226 p2dr port 2 data register ff r228 p4dr port 4 data register ff r229 p5dr port 5 data register ff 0 int r242 eitr external interrupt trigger register 00 52 r243 eipr external interrupt pending reg. 00 53 r244 eimr external interrupt mask-bit reg. 00 53 r245 eiplr external interrupt priority level reg. ff 53 r246 eivr external interrupt vector register x6 54 r247 nicr nested interrupt control 00 54 wdt r248 wdthr watchdog timer high register ff 90 r249 wdtlr watchdog timer low register ff 90 r250 wdtpr watchdog timer prescaler reg. ff 90 r251 wdtcr watchdog timer control register 12 90 r252 wcr wait control register 7f 91 2 i/o port 3 r252 p3c0 port 3 configuration register 0 00 79 r253 p3c1 port 3 configuration register 1 00 r254 p3c2 port 3 configuration register 2 00 3 i/o port 5 r244 p5c0 port 5 configuration register 0 ff r245 p5c1 port 5 configuration register 1 00 r246 p5c2 port 5 configuration register 2 00 7spi r240 spdr spi data register 00 145 r241 spcr spi control register 00 145 r242 spsr spi status register 00 146 r243 sppr spi prescaler register 00 146 11 stim r240 sth counter high byte register ff 95 r241 stl counter low byte register ff 95 r242 stp standard timer prescaler register ff 95 r243 stc standard timer control register 14 95 9
18/179 st92141 - general description 21 mmu r240 dpr0 data page register 0 xx 35 r241 dpr1 data page register 1 xx 35 r242 dpr2 data page register 2 xx 35 r243 dpr3 data page register 3 xx 35 r244 csr code segment register 00 36 r248 isr interrupt segment register xx 36 r249 dmasr dma segment register xx 36 em r245 emr1 em register 1 80 62 r246 emr2 em register 2 0f 62 28 eft r240 ic1hr input capture 1 high register xx 108 r241 ic1lr input capture 1 low register xx 108 r242 ic2hr input capture 2 high register xx 108 r243 ic2lr input capture 2 low register xx 108 r244 chr counter high register ff 109 r245 clr counter low register fc 109 r246 achr alternate counter high register ff 109 r247 aclr alternate counter low register fc 109 r248 oc1hr output compare 1 high register 80 110 r249 oc1lr output compare 1 low register 00 110 r250 oc2hr output compare 2 high register 80 110 r251 oc2lr output compare 2 low register 00 110 r252 cr1 control register 1 00 111 r253 cr2 control register 2 00 112 r254 sr status register 00 113 r255 cr3 control register 3 00 113 48 imc r248 pcr0 peripheral control register 0 80 130 r249 pcr1 peripheral control register 1 00 130 r250 pcr2 peripheral control register 2 00 131 r251 psr polarity selection register 00 131 r252 opr output peripheral register 00 132 r253 imr interrupt mask register 00 132 r254 dtg dead time generator register 00 133 r255 imcivr imc interrupt vector register xx 133 page (decimal) block reg. no. register name description reset value hex. doc. page 9
19/179 st92141 - general description note: xx denotes a byte with an undefined value, however some of the bits may have defined values. refer to register description for details. 51 imc r240 tcpth tacho capture register high xx 125 r241 tcptl tacho capture register low xx 125 r242 tcmp tacho compare register xx 125 r243 isr interrupt status register 3f 36 r244 tprsh tacho prescaler register high 00 127 r245 tprsl tacho prescaler register low 00 127 r246 cprs pwm counter prescaler register 00 127 r247 rep repetition counter register 00 127 r248 cpwh compare phase w preload register high 00 128 r249 cpwl compare phase w preload register low 00 128 r250 cpvh compare phase v preload register high 00 128 r251 cpvl compare phase v preload register low 00 128 r252 cpuh compare phase u preload register high 00 129 r253 cpul compare phase u preload register low 00 129 r254 cp0h compare 0 preload register high 00 129 r255 cp0l compare 0 preload register low 00 129 55 rccu r240 clkctl clock control register 00 69 r242 clk_flag clock flag register 48, 28 70 r246 pllconf pll configuration register xx 71 57 wuimu r249 wuctrl wake-up control register 00 59 r250 wumrh wake-up mask register high 00 60 r251 wumrl wake-up mask register low 00 60 r252 wutrh wake-up trigger register high 00 61 r253 wutrl wake-up trigger register low 00 61 r254 wuprh wake-up pending register high 00 61 r255 wuprl wake-up pending register low 00 61 63 adc r240 d0r channel 0 data register xx 151 r241 d1r channel 1 data register xx 151 r242 d2r channel 2 data register xx 151 r243 d3r channel 3 data register xx 151 r244 d4r channel 4 data register xx 151 r245 d5r channel 5 data register xx 151 r246 d6r channel 6 data register xx 151 r247 d7r channel 7 data register xx 151 r248 lt6r channel 6 lower threshold reg. xx 152 r249 lt7r channel 7 lower threshold reg. xx 152 r250 ut6r channel 6 upper threshold reg. xx 152 r251 ut7r channel 7 upper threshold reg. xx 152 r252 crr compare result register 0f 153 r253 clr control logic register 00 154 r254 icr interrupt control register 0f 155 r255 ivr interrupt vector register x2 155 page (decimal) block reg. no. register name description reset value hex. doc. page 9
20/179 st92141 - device architecture 2 device architecture 2.1 core architecture the st9 core or central processing unit (cpu) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as bcd and boolean formats; 14 address- ing modes are available. four independent buses are controlled by the core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit in- terrupt/dma bus which connects the interrupt and dma controllers in the on-chip peripherals with the core. this multiple bus architecture affords a high de- gree of pipelining and parallel operation, thus mak- ing the st9 family devices highly efficient, both for numerical calculation, data handling and with re- gard to communication with on-chip peripheral re- sources. 2.2 memory spaces there are two separate memory spaces: C the register file, which comprises 240 8-bit registers, arranged as 15 groups (group 0 to e), each containing sixteen 8-bit registers plus up to 64 pages of 16 registers mapped in group f, which hold data and control bits for the on-chip peripherals and i/os. C a single linear memory space accommodating both program and data. all of the physically sep- arate memory areas, including the internal rom, internal ram and external memory are mapped in this common address space. the total ad- dressable memory space of 4 mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 seg- ments of 64 kbytes. each segment is further subdivided into four pages of 16 kbytes, as illus- trated in figure 3 . a memory management unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instruc- tions. 2.2.1 register file the register file consists of (see figure 4 ): C 224 general purpose registers (group 0 to d, registers r0 to r223) C 6 system registers in the system group (group e, registers r224 to r239) C up to 64 pages, depending on device configura- tion, each containing up to 16 registers, mapped to group f (r240 to r255), see figure 5 . figure 3. single program and data memory address space 3fffffh 3f0000h 3effffh 3e0000h 20ffffh 02ffffh 020000h 01ffffh 010000h 00ffffh 000000h 8 7 6 5 4 3 2 1 0 63 62 2 1 0 address 16k pages 64k segments up to 4 mbytes data code 255 254 253 252 251 250 249 248 247 9 10 11 21ffffh 210000h 133 134 135 33 reserved 132 9
21/179 st92141 - device architecture memory spaces (contd) figure 4. register groups figure 5. page pointer for group f mapping figure 6. addressing the register file f e d c b a 9 8 7 6 5 4 3 paged registers system registers 2 1 0 00 15 255 240 239 224 223 va00432 up to 64 pages general registers purpose 224 page 63 page 5 page 0 page pointer r255 r240 r224 r0 va00433 r234 register file system registers group d group b group c (1100) (0011) r192 r207 255 240 239 224 223 f e d c b a 9 8 7 6 5 4 3 2 1 0 15 vr000118 00 r195 r195 (r0c3h) paged registers 9
22/179 st92141 - device architecture memory spaces (contd) 2.2.2 register addressing register file registers, including group f paged registers (but excluding group d), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus r231, re7h and r11100111b represent the same register (see figure 6 ). group d registers can only be ad- dressed in working register mode. note that an upper case r is used to denote this direct addressing mode. working registers certain types of instruction require that registers be specified in the form rx , where x is in the range 0 to 15: these are known as working regis- ters. note that a lower case r is used to denote this in- direct addressing mode. two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working reg- isters. these groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. this tech- nique is described in more detail in section 2.3.3 register pointing techniques, and illustrated in figure 7 and in figure 8 . system registers the 16 registers in group e (r224 to r239) are system registers and may be addressed using any of the register addressing modes. these registers are described in greater detail in section 2.3 sys- tem registers. paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these are addressed us- ing any register addressing mode, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. therefore if the page pointer, r234, is set to 5, the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). these paged registers hold data and control infor- mation relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these regis- ters therefore depends on the peripherals which are present in the specific st9 family device. in other words, pages only exist if the relevant pe- ripheral is present. table 9. register file organization hex. address decimal address function register file group f0-ff 240-255 paged registers group f e0-ef 224-239 system registers group e d0-df 208-223 general purpose registers group d c0-cf 192-207 group c b0-bf 176-191 group b a0-af 160-175 group a 90-9f 144-159 group 9 80-8f 128-143 group 8 70-7f 112-127 group 7 60-6f 96-111 group 6 50-5f 80-95 group 5 40-4f 64-79 group 4 30-3f 48-63 group 3 20-2f 32-47 group 2 10-1f 16-31 group 1 00-0f 00-15 group 0 1
23/179 st92141 - device architecture 2.3 system registers the system registers are listed in table 10 sys- tem registers (group e) . they are used to per- form all the important system settings. their pur- pose is described in the following pages. refer to the chapter dealing with i/o for a description of the port[5:0] data registers. table 10. system registers (group e) 2.3.1 central interrupt control register please refer to the interrupt chapter for a de- tailed description of the st9 interrupt philosophy. central interrupt control register (cicr) r230 - read/write register group: e (system) reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable . this bit is the global counter enable of the multi- function timers. the gcen bit is anded with the ce bit in the tcr register (only in devices featur- ing the mft multifunction timer) in order to enable the timers when both bits are set. this bit is set af- ter the reset cycle. note: if an mft is not included in the st9 device, then this bit has no effect. bit 6 = tlip : top level interrupt pending . this bit is set by hardware when a top level inter- rupt request is recognized. this bit can also be set by software to simulate a top level interrupt request. 0: no top level interrupt pending 1: top level interrupt pending bit 5 = tli : top level interrupt bit . 0: top level interrupt is acknowledged depending on the tlnm bit in the nicr register. 1: top level interrupt is acknowledged depending on the ien and tlnm bits in the nicr register (described in the interrupt chapter). bit 4 = ien : interrupt enable . this bit is cleared by interrupt acknowledgement, and set by interrupt return ( iret ). ien is modified implicitly by iret , ei and di instructions or by an interrupt acknowledge cycle. it can also be explic- itly written by the user, but only when no interrupt is pending. therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the cicr register. 0: disable all interrupts except top level interrupt. 1: enable interrupts bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software to select the arbitration mode. 0: concurrent mode 1: nested mode. bits 2:0 = cpl[2:0] : current priority level . these three bits record the priority level of the rou- tine currently running (i.e. the current priority lev- el, cpl). the highest priority level is represented by 000, and the lowest by 111. the cpl bits can be set by hardware or software and provide the reference according to which subsequent inter- rupts are either left pending or are allowed to inter- rupt the current interrupt service routine. when the current interrupt is replaced by one of a higher pri- ority, the current priority value is automatically stored until required in the nicr register. r239 (efh) ssplr r238 (eeh) ssphr r237 (edh) usplr r236 (ech) usphr r235 (ebh) mode register r234 (eah) page pointer register r233 (e9h) register pointer 1 r232 (e8h) register pointer 0 r231 (e7h) flag register r230 (e6h) central int. cntl reg r229 (e5h) port5 data reg. r228 (e4h) port4 data reg. r227 (e3h) port3 data reg. r226 (e2h) port2 data reg. r225 (e1h) port1 data reg. r224 (e0h) port0 data reg. 70 gcen tlip tli ien iam cpl2 cpl1 cpl0 1
24/179 st92141 - device architecture system registers (contd) 2.3.2 flag register the flag register contains 8 flags which indicate the cpu status. during an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the cpu to its original status. this occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. flag register (flagr) r231- read/write register group: e (system) reset value: 0000 0000 (00h ) bit 7 = c : carry flag . the carry flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate ( rrc, rrcw, rlc, rlcw, ror, rol ), decimal adjust ( da ), multiply and divide ( mul, div, divws ). when set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). the carry flag can be set by the set carry flag ( scf ) instruction, cleared by the reset carry flag ( rcf ) instruction, and complemented by the com- plement carry flag ( ccf ) instruction. bit 6 = z: zero flag . the zero flag is affected by: addition ( add, addw, adc, adcw ), subtraction ( sub, subw, sbc, sbcw ), compare ( cp, cpw ), shift right arithmetic ( sra, sraw ), shift left arithmetic ( sla, slaw ), swap nibbles ( swap ), rotate (rrc , rrcw, rlc, rlcw, ror, rol) , decimal adjust ( da ), multiply and divide ( mul, div, divws ), logical ( and, andw, or, orw, xor, xorw, cpl ), increment and decrement ( inc, incw, dec, decw ), test ( tm, tmw, tcm, tcmw, btset ). in most cases, the zero flag is set when the contents of the register being used as an accumulator be- come zero, following one of the above operations. bit 5 = s : sign flag . the sign flag is affected by the same instructions as the zero flag. the sign flag is set when bit 7 (for a byte opera- tion) or bit 15 (for a word operation) of the register used as an accumulator is one. bit 4 = v : overflow flag . the overflow flag is affected by the same instruc- tions as the zero and sign flags. when set, the overflow flag indicates that a two's- complement number, in a result register, is in er- ror, since it has exceeded the largest (or is less than the smallest), number that can be represent- ed in twos-complement notation. bit 3 = da : decimal adjust flag . the da flag is used for bcd arithmetic. since the algorithm for correcting bcd operations is differ- ent for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent decimal adjust ( da ) operation can perform its function correctly. the da flag cannot normally be used as a test condi- tion by the programmer. bit 2 = h : half carry flag. the h flag indicates a carry out of (or a borrow in- to) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two bcd digits. the h flag is used by the decimal adjust ( da ) instruc- tion to convert the binary result of a previous addi- tion or subtraction into the correct bcd result. like the da flag, this flag is not normally accessed by the user. bit 1 = reserved bit (must be 0). bit 0 = dp : data/program memory flag . this bit indicates the memory area addressed. its value is affected by the set data memory ( sdm ) and set program memory ( spm ) instructions. re- fer to the memory management unit for further de- tails. 70 c z s v da h - dp 1
25/179 st92141 - device architecture system registers (contd) if the bit is set, data is accessed using the data pointers (dprs registers), otherwise it is pointed to by the code pointer (csr register); therefore, the user initialization routine must include a sdm instruction. note that code is always pointed to by the code pointer (csr). note: in the current st9 devices, the dp flag is only for compatibility with software developed for the first generation of st9 devices. with the single memory addressing space, its use is now redun- dant. it must be kept to 1 with a sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers. 2.3.3 register pointing techniques two registers within the system register group, are used as pointers to the working registers. reg- ister pointer 0 (r232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with register pointer 1 (r233), to point to two separate 8-register spaces. for the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8- register blocks. the values specified with the set register pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the low- er 8-register block location in single 16-register mode. the set register pointer instructions srp , srp0 and srp1 automatically inform the cpu whether the register file is to operate in single 16-register mode or in twin 8-register mode. the srp instruc- tion selects the single 16-register group mode and specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block. there is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16- register mode. the block number should always be an even number in single 16-register mode. the 16-regis- ter group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. thus: srp #3 will be interpreted as srp #2 and will al- low using r16 ..r31 as r0 .. r15. in single 16-register mode, the working registers are referred to as r0 to r15 . in twin 8-register mode, registers r0 to r7 are in the block pointed to by rp0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by rp1 (by means of the srp1 instruction). caution : group d registers can only be accessed as working registers using the register pointers, or by means of the stack pointers. they cannot be addressed explicitly in the form rxxx . 1
26/179 st92141 - device architecture system registers (contd) pointer 0 register (rp0) r232 - read/write register group: e (system) reset value: xxxx xx00 (xxh) bits 7:3 = rg[4:0] : register group number. these bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. in single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0: reserved. forced by hardware to zero. pointer 1 register (rp1) r233 - read/write register group: e (system) reset value: xxxx xx00 (xxh) this register is only used in the twin register point- ing mode. when using the single register pointing mode, or when using only one of the twin register groups, the rp1 register must be considered as reserved and may not be used as a general purpose register. bits 7:3 = rg[4:0]: register group number. these bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 in- struction, to which r8 to r15 are to be mapped. bit 2 = rps : register pointer selector . this bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is se- lected. the bit is reset by the srp instruction to in- dicate that the single register pointing mode is se- lected. 0: single register pointing mode 1: twin register pointing mode bits 1:0: reserved. forced by hardware to zero. 70 rg4 rg3 rg2 rg1 rg0 rps 0 0 70 rg4 rg3 rg2 rg1 rg0 rps 0 0 1
27/179 st92141 - device architecture system registers (contd) figure 7. pointing to a single group of 16 registers figure 8. pointing to two groups of 8 registers 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp #2 set by: instruction points to: group 1 addressed by block 2 r15 r0 31 30 29 28 27 26 25 9 8 7 6 5 4 3 2 1 0 f e d 4 3 2 1 0 block number register group register file register pointer 0 srp0 #2 set by: instructions point to: group 1 addressed by block 2 & register pointer 1 srp1 #7 & group 3 addressed by block 7 r7 r0 r15 r8 1
28/179 st92141 - device architecture system registers (contd) 2.3.4 paged registers up to 64 pages, each containing 16 registers, may be mapped to group f. these paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between st9 devices. the number of these registers depends on the pe- ripherals present in the specific st9 device. in oth- er words, pages only exist if the relevant peripher- al is present. the paged registers are addressed using the nor- mal register addressing modes, in conjunction with the page pointer register, r234, which is one of the system registers. this register selects the page to be mapped to group f and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. thus the instructions: spp #5 ld r242, r4 will load the contents of working register r4 into the third register of page 5 (r242). warning: during an interrupt, the ppr register is not saved automatically in the stack. if needed, it should be saved/restored by the user within the in- terrupt routine. page pointer register (ppr) r234 - read/write register group: e (system) reset value: xxxx xx00 (xxh ) bits 7:2 = pp[5:0] : page pointer . these bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. once the page pointer has been set, there is no need to refresh it unless a different page is re- quired. bits 1:0: reserved. forced by hardware to 0. 2.3.5 mode register the mode register allows control of the following operating parameters: C selection of internal or external system and user stack areas, C management of the clock frequency, C enabling of bus request and wait signals when interfacing to external memory. mode register (moder) r235 - read/write register group: e (system) reset value: 1110 0000 (e0h) bit 7 = ssp : system stack pointer . this bit selects an internal or external system stack area. 0: external system stack area, in memory space. 1: internal system stack area, in the register file (reset state). bit 6 = usp : user stack pointer . this bit selects an internal or external user stack area. 0: external user stack area, in memory space. 1: internal user stack area, in the register file (re- set state). bit 5 = div2 : crystal oscillator clock divided by 2 . this bit controls the divide-by-2 circuit operating on the crystal oscillator clock (clock1). 0: clock divided by 1 1: clock divided by 2 bits 4:2 = prs[2:0] : cpuclk prescaler . these bits load the prescaler division factor for the internal clock (intclk). the prescaler factor se- lects the internal clock frequency, which can be di- vided by a factor from 1 to 8. refer to the reset and clock control chapter for further information. bit 1 = brqen : bus request enable . 0: external memory bus request disabled 1: external memory bus request enabled on breq pin (where available). note: disregard this bit if breq pin is not availa- ble. bit 0 = himp : high impedance enable . when any of ports 0, 1, 2 or 6 depending on de- vice configuration, are programmed as address and data lines to interface external memory, these lines and the memory interface control lines (as, ds, r/w) can be forced into the high impedance 70 pp5 pp4 pp3 pp2 pp1 pp0 0 0 70 ssp usp div2 prs2 prs1 prs0 brqen himp 1
29/179 st92141 - device architecture system registers (contd) state by setting the himp bit. when this bit is reset, it has no effect. setting the himp bit is recommended for noise re- duction when only internal memory is used. if port 1 and/or 2 are declared as an address and as an i/o port (for example: p10... p14 = address, and p15... p17 = i/o), the himp bit has no effect on the i/o lines. 2.3.6 stack pointers two separate, double-register stack pointers are available: the system stack pointer and the user stack pointer, both of which can address registers or memory. the stack pointers point to the bottom of the stacks which are f illed using the push commands and emptied using the pop commands. the stack pointer is automatically pre-decremented when data is pushed in and post-incremented when data is popped out. the push and pop commands used to manage the system stack may be addressed to the user stack by adding the suffix u . to use a stack in- struction for a word, the suffix w is added. these suffixes may be combined. when bytes (or words) are popped out from a stack, the contents of the stack locations are un- changed until fresh data is loaded. thus, when data is popped from a stack area, the stack con- tents remain unchanged. note: instructions such as: pushuw rr236 or pushw rr238, as well as the corresponding pop instructions (where r236 & r237, and r238 & r239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus cor- rupting their value. system stack the system stack is used for the temporary stor- age of system and/or control data, such as the flag register and the program counter. the following automatically push data onto the system stack: C interrupts when entering an interrupt, the pc and the flag register are pushed onto the system stack. if the encsr bit in the emr2 register is set, then the code segment register is also pushed onto the system stack. C subroutine calls when a call instruction is executed, only the pc is pushed onto stack, whereas when a calls in- struction (call segment) is executed, both the pc and the code segment register are pushed onto the system stack. C link instruction the link or linku instructions create a c lan- guage stack frame of user-defined length in the system or user stack. all of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. user stack the user stack provides a totally user-controlled stacking area. the user stack pointer consists of two registers, r236 and r237, which are both used for address- ing a stack in memory. when stacking in the reg- ister file, the user stack pointer high register, r236, becomes redundant but must be consid- ered as reserved. stack pointers both system and user stacks are pointed to by double-byte stack pointers. stacks may be set up in ram or in the register file. only the lower byte will be required if the stack is in the register file. the upper byte must then be considered as re- served and must not be used as a general purpose register. the stack pointer registers are located in the sys- tem group of the register file, this is illustrated in table 10 system registers (group e) . stack location care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. consequently programmers are advised to use a stack pointer value as high as possible, particular- ly when using the register file as a stacking area. group d is a good location for a stack in the reg- ister file, since it is the highest available area. the stacks may be located anywhere in the first 14 groups of the register file (internal stacks) or in ram (external stacks). note . stacks must not be located in the paged register group or in the system register group. 1
30/179 st92141 - device architecture system registers (contd) user stack pointer high register (usphr) r236 - read/write register group: e (system) reset value: undefined user stack pointer low register (usplr) r237 - read/write register group: e (system) reset value: undefined figure 9. internal stack mode system stack pointer high register (ssphr) r238 - read/write register group: e (system) reset value: undefined system stack pointer low register (ssplr) r239 - read/write register group: e (system) reset value: undefined figure 10. external stack mode 70 usp15 usp14 usp13 usp12 usp11 usp10 usp9 usp8 70 usp7 usp6 usp5 usp4 usp3 usp2 usp1 usp0 f e d 4 3 2 1 0 register file stack pointer (low) points to: stack 70 ssp15 ssp14 ssp13 ssp12 ssp11 ssp10 ssp9 ssp8 70 ssp7 ssp6 ssp5 ssp4 ssp3 ssp2 ssp1 ssp0 f e d 4 3 2 1 0 register file stack pointer (low) point to: stack memory stack pointer (high) & 1
31/179 st92141 - device architecture 2.4 memory organization code and data are accessed within the same line- ar address space. all of the physically separate memory areas, including the internal rom, inter- nal ram and external memory are mapped in a common address space. the st9 provides a total addressable memory space of 4 mbytes. this address space is ar- ranged as 64 segments of 64 kbytes; each seg- ment is again subdivided into four 16 kbyte pages. the mapping of the various memory areas (inter- nal ram or rom, external memory) differs from device to device. each 64-kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 kbytes, the remaining locations in the 64-kbyte segment are not used (reserved). refer to the register and memory map chapter for more details on the memory map. 1
32/179 st92141 - device architecture 2.5 memory management unit the cpu core includes a memory management unit (mmu) which must be programmed to per- form memory accesses (even if external memory is not used). the mmu is controlled by 7 registers and 2 bits (encsr and dprrem) present in emr2, which may be written and read by the user program. these registers are mapped within group f, page 21 of the register file. the 7 registers may be sub-divided into 2 main groups: a first group of four 8-bit registers (dpr[3:0]), and a second group of three 6-bit registers (csr, isr, and dmasr). the first group is used to extend the address during data memory access (dpr[3:0]). the second is used to manage program and data memory ac- cesses during code execution (csr), interrupts service routines (isr or csr), and dma trans- fers (dmasr or isr). figure 11. page 21 registers dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 r255 r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 r240 ffh feh fdh fch fbh fah f9h f8h f7h f6h f5h f4h f3h f2h f1h f0h mmu em page 21 mmu mmu bit dprrem=0 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 1 dpr0 bit dprrem=1 ssplr ssphr usplr usphr moder ppr rp1 rp0 flagr cicr p5dr p4dr p3dr p2dr p1dr p0dr dmasr isr emr2 emr1 csr dpr3 dpr2 dpr1 dpr0 relocation of p[3:0] and dpr[3:0] registers (default setting) 1
33/179 st92141 - device architecture 2.6 address space extension to manage 4 mbytes of addressing space, it is necessary to have 22 address bits. the mmu adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical address. there are 2 different ways to do this de- pending on the memory involved and on the oper- ation being performed. 2.6.1 addressing 16-kbyte pages this extension mode is implicitly used to address data memory space if no dma is being performed. the data memory space is divided into 4 pages of 16 kbytes. each one of the four 8-bit registers (dpr[3:0], data page registers) selects a differ- ent 16-kbyte page. the dpr registers allow ac- cess to the entire memory space which contains 256 pages of 16 kbytes. data paging is performed by extending the 14 lsb of the 16-bit address with the contents of a dpr register. the two msbs of the 16-bit address are interpreted as the identification number of the dpr register to be used. therefore, the dpr registers are involved in the following virtual address rang- es: dpr0: from 0000h to 3fffh; dpr1: from 4000h to 7fffh; dpr2: from 8000h to bfffh; dpr3: from c000h to ffffh. the contents of the selected dpr register specify one of the 256 possible data memory pages. this 8-bit data page number, in addition to the remain- ing 14-bit page offset address forms the physical 22-bit address (see figure 12 ). a dpr register cannot be modified via an address- ing mode that uses the same dpr register. for in- stance, the instruction popw dpr0 is legal only if the stack is kept either in the register file or in a memory location above 8000h, where dpr2 and dpr3 are used. otherwise, since dpr0 and dpr1 are modified by the instruction, unpredicta- ble behaviour could result. figure 12. addressing via dpr[3:0] dpr0 dpr1 dpr2 dpr3 00 01 10 11 16-bit virtual address 22-bit physical address 8 bits mmu registers 2 m sb 14 lsb 1
34/179 st92141 - device architecture address space extension (contd) 2.6.2 addressing 64-kbyte segments this extension mode is used to address data memory space during a dma and program mem- ory space during any code execution (normal code and interrupt routines). three registers are used: csr, isr, and dmasr. the 6-bit contents of one of the registers csr, isr, or dmasr define one out of 64 memory seg- ments of 64 kbytes within the 4 mbytes address space. the register contents represent the 6 msbs of the memory address, whereas the 16 lsbs of the address (intra-segment address) are given by the virtual 16-bit address (see figure 13 ). 2.7 mmu registers the mmu uses 7 registers mapped into group f, page 21 of the register file and 2 bits of the emr2 register. most of these registers do not have a default value after reset. 2.7.1 dpr[3:0]: data page registers the dpr[3:0] registers allow access to the entire 4 mbyte memory space composed of 256 pages of 16 kbytes. 2.7.1.1 data page register relocation if these registers are to be used frequently, they may be relocated in register group e, by program- ming bit 5 of the emr2-r246 register in page 21. if this bit is set, the dpr[3:0] registers are located at r224-227 in place of the port 0-3 data registers, which are re-mapped to the default dpr's loca- tions: r240-243 page 21. data page register relocation is illustrated in fig- ure 11 . figure 13. addressing via csr, isr, and dmasr fetching program data memory fetching interrupt instruction accessed in dma instruction or dma access to program memory 16-bit virtual address 22-bit physical address 6 bits mmu registers csr isr dmasr 1 2 3 1 2 3 1
35/179 st92141 - device architecture mmu registers (contd) data page register 0 (dpr0) r240 - read/write register page: 21 reset value: undefined this register is relocated to r224 if emr2.5 is set. bits 7:0 = dpr0_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr0 register is used when addressing the virtual address range 0000h-3fffh. data page register 1 (dpr1) r241 - read/write register page: 21 reset value: undefined this register is relocated to r225 if emr2.5 is set. bits 7:0 = dpr1_[7:0] : these bits define the 16- kbyte data memory page number. they are used as the most significant address bits (a21-14) to ex- tend the address during a data memory access. the dpr1 register is used when addressing the virtual address range 4000h-7fffh. data page register 2 (dpr2) r242 - read/write register page: 21 reset value: undefined this register is relocated to r226 if emr2.5 is set. bits 7:0 = dpr2_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr2 register is involved when the virtual address is in the range 8000h-bfffh. data page register 3 (dpr3) r243 - read/write register page: 21 reset value: undefined this register is relocated to r227 if emr2.5 is set. bits 7:0 = dpr3_[7:0] : these bits define the 16- kbyte data memory page. they are used as the most significant address bits (a21-14) to extend the address during a data memory access. the dpr3 register is involved when the virtual address is in the range c000h-ffffh. 70 dpr0_7 dpr0_6 dpr0_5 dpr0_4 dpr0_3 dpr0_2 dpr0_1 dpr0_0 70 dpr1_7 dpr1_6 dpr1_5 dpr1_4 dpr1_3 dpr1_2 dpr1_1 dpr1_0 70 dpr2_7 dpr2_6 dpr2_5 dpr2_4 dpr2_3 dpr2_2 dpr2_1 dpr2_0 70 dpr3_7 dpr3_6 dpr3_5 dpr3_4 dpr3_3 dpr3_2 dpr3_1 dpr3_0 1
36/179 st92141 - device architecture mmu registers (contd) 2.7.2 csr: code segment register this register selects the 64-kbyte code segment being used at run-time to access instructions. it can also be used to access data if the spm instruc- tion has been executed (or ldpp, ldpd, lddp ). only the 6 lsbs of the csr register are imple- mented, and bits 6 and 7 are reserved. the csr register allows access to the entire memory space, divided into 64 segments of 64 kbytes. to generate the 22-bit program memory address, the contents of the csr register is directly used as the 6 msbs, and the 16-bit virtual address as the 16 lsbs. note: the csr register should only be read and not written for data operations (there are some ex- ceptions which are documented in the following paragraph). it is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets in- struction. code segment register (csr) r244 - read/write register page: 21 reset value: 0000 0000 (00h) bits 7:6 = reserved, keep in reset state. bits 5:0 = csr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the code being executed. these bits are used as the most significant address bits (a21-16). 2.7.3 isr: interrupt segment register interrupt segment register (isr) r248 - read/write register page: 21 reset value: undefined isr and encsr bit (emr2 register) are also de- scribed in the chapter relating to interrupts, please refer to this description for further details. bits 7:6 = reserved, keep in reset state. bits 5:0 = isr_[5:0] : these bits define the 64- kbyte memory segment (among 64) which con- tains the interrupt vector table and the code for in- terrupt service routines and dma transfers (when the ps bit of the dapr register is reset). these bits are used as the most significant address bits (a21-16). the isr is used to extend the address space in two cases: C whenever an interrupt occurs: isr points to the 64-kbyte memory segment containing the inter- rupt vector table and the interrupt service routine code. see also the interrupts chapter. C during dma transactions between the peripheral and memory when the ps bit of the dapr regis- ter is reset : isr points to the 64 k-byte memory segment that will be involved in the dma trans- action. 2.7.4 dmasr: dma segment register dma segment register (dmasr) r249 - read/write register page: 21 reset value: undefined bits 7:6 = reserved, keep in reset state. bits 5:0 = dmasr_[5:0] : these bits define the 64- kbyte memory segment (among 64) used when a dma transaction is performed between the periph- eral's data register and memory, with the ps bit of the dapr register set. these bits are used as the most significant address bits (a21-16). if the ps bit is reset, the isr register is used to extend the ad- dress. 70 00 csr_5 csr_4 csr_3 csr_2 csr_1 csr_0 70 0 0 isr_5 isr_4 isr_3 isr_2 isr_1 isr_0 70 00 dma sr_5 dma sr_4 dma sr_3 dma sr_2 dma sr_1 dma sr_0 1
37/179 st92141 - device architecture mmu registers (contd) figure 14. memory addressing scheme (example) 3fffffh 294000h 240000h 23ffffh 20c000h 200000h 1fffffh 040000h 03ffffh 030000h 020000h 010000h 00c000h 000000h dmasr isr csr dpr3 dpr2 dpr1 dpr0 4m bytes 16k 16k 16k 64k 64k 64k 16k 1
38/179 st92141 - device architecture 2.8 mmu usage 2.8.1 normal program execution program memory is organized as a set of 64- kbyte segments. the program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps , calls and rets instructions, which automatically modify the csr, must be used to jump across segment boundaries. writing to the csr is forbidden during normal program execution because it is not syn- chronized with the opcode fetch. this could result in fetching the first byte of an instruction from one memory segment and the second byte from anoth- er. writing to the csr is allowed when it is not be- ing used, i.e during an interrupt service routine if encsr is reset. note that a routine must always be called in the same way, i.e. either always with call or always with calls , depending on whether the routine ends with ret or rets . this means that if the rou- tine is written without prior knowledge of the loca- tion of other routines which call it, and all the pro- gram code does not fit into a single 64-kbyte seg- ment, then calls / rets should be used. in typical microcontroller applications, less than 64 kbytes of ram are used, so the four data space pages are normally sufficient, and no change of dpr[3:0] is needed during program execution. it may be useful however to map part of the rom into the data space if it contains strings, tables, bit maps, etc. if there is to be frequent use of paging, the user can set bit 5 (dprrem) in register r246 (emr2) of page 21. this swaps the location of registers dpr[3:0] with that of the data registers of ports 0- 3. in this way, dpr registers can be accessed without the need to save/set/restore the page pointer register. port registers are therefore moved to page 21. applications that require a lot of paging typically use more than 64 kbytes of exter- nal memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 interrupts the isr register has been created so that the in- terrupt routines may be found by means of the same vector table even after a segment jump/call. when an interrupt occurs, the cpu behaves in one of 2 ways, depending on the value of the enc- sr bit in the emr2 register (r246 on page 21). if this bit is reset (default condition), the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, the isr is used instead of the csr, and the interrupt stack frame is kept exactly as in the original st9 (only the pc and flags are pushed). this avoids the need to save the csr on the stack in the case of an interrupt, ensuring a fast interrupt response time. the drawback is that it is not possible for an interrupt service routine to perform segment calls / jps : these instructions would update the csr, which, in this case, is not used (isr is used instead). the code size of all interrupt service rou- tines is thus limited to 64 kbytes. if, instead, bit 6 of the emr2 register is set, the isr is used only to point to the interrupt vector ta- ble and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and the flags, and then the csr is loaded with the isr. in this case, an iret will also restore the csr from the stack. this approach lets interrupt service routines access the whole 4-mbyte address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save the csr on the stack. compatibility with the original st9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast major- ity of programs. data memory mapping is independent of the value of bit 6 of the emr2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the st9. if the interrupt service routine needs to access additional data memory, it must save one (or more) of the dprs, load it with the needed memory page and restore it before completion. 2.8.3 dma depending on the ps bit in the dapr register (see dma chapter) dma uses either the isr or the dmasr for memory accesses: this guarantees that a dma will always find its memory seg- ment(s), no matter what segment changes the ap- plication has performed. unlike interrupts, dma transactions cannot save/restore paging registers, so a dedicated segment register (dmasr) has been created. having only one register of this kind means that all dma accesses should be pro- grammed in one of the two following segments: the one pointed to by the isr (when the ps bit of the dapr register is reset), and the one refer- enced by the dmasr (when the ps bit is set). 1
39/179 st92141 - interrupts 3 interrupts 3.1 introduction the st9 responds to peripheral and external events through its interrupt channels. current pro- gram execution can be suspended to allow the st9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. if an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate interrupt service routine (refer to figure 15 ). the st9 cpu can receive requests from the fol- lowing sources: C on-chip peripherals C external pins C top-level pseudo-non-maskable interrupt according to the on-chip peripheral features, an event occurrence can generate an interrupt re- quest which depends on the selected mode. up to eight external interrupt channels, with pro- grammable input trigger edge, are available. in ad- dition, a dedicated interrupt channel, set to the top-level priority, can be devoted either to the ex- ternal nmi pin (where available) to provide a non- maskable interrupt, or to the timer/watchdog. in- terrupt service routines are addressed through a vector table mapped in memory. figure 15. interrupt response n 3.2 interrupt vectoring the st9 implements an interrupt vectoring struc- ture which allows the on-chip peripheral to identify the location of the first instruction of the interrupt service routine automatically. when an interrupt request is acknowledged, the peripheral interrupt module provides, through its interrupt vector register (ivr), a vector to point into the vector table of locations containing the start addresses of the interrupt service routines (defined by the programmer). each peripheral has a specific ivr mapped within its register file pages. the interrupt vector table, containing the address- es of the interrupt service routines, is located in the first 256 locations of memory pointed to by the isr register, thus allowing 8-bit vector addressing. for a description of the isr register refer to the chapter describing the mmu. the user power on reset vector is stored in the first two physical bytes in memory, 000000h and 000001h. the top level interrupt vector is located at ad- dresses 0004h and 0005h in the segment pointed to by the interrupt segment register (isr). with one interrupt vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. the most significant bits of the vector are user pro- grammable to define the base vector address with- in the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. note : the first 256 locations of the memory seg- ment pointed to by isr can contain program code. 3.2.1 divide by zero trap the divide by zero trap vector is located at ad- dresses 0002h and 0003h of each code segment; it should be noted that for each code segment a divide by zero service routine is required. warning . although the divide by zero trap oper- ates as an interrupt, the flag register is not pushed onto the system stack automatically. as a result it must be regarded as a subroutine, and the service routine must end with the ret instruction (not iret ). normal program flow interrupt service routine iret instruction interrupt vr001833 clear pending bit 1
40/179 st92141 - interrupts 3.2.2 segment paging during interrupt routines the encsr bit in the emr2 register can be used to select between original st9 backward compati- bility mode and st9+ interrupt management mode. st9 backward compatibility mode (encsr = 0) if encsr is reset, the cpu works in original st9 compatibility mode. for the duration of the inter- rupt service routine, isr is used instead of csr, and the interrupt stack frame is identical to that of the original st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster inter- rupt response time. it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service routines is thus limited to 64k bytes. st9+ mode (encsr = 1) if encsr is set, isr is only used to point to the in- terrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the con- tents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service rou- tines to access the entire 4 mbytes of address space. the drawback is that the interrupt response time is slightly increased, because of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is differ- ent. 3.3 interrupt priority levels the st9 supports a fully programmable interrupt priority structure. nine priority levels are available to define the channel priority relationships: C the on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. each channel has a 3- bit field, prl (priority level), that defines its pri- ority level in the range from 0 (highest priority) to 7 (lowest priority). C the 9th level (top level priority) is reserved for the timer/watchdog or the external pseudo non-maskable interrupt. an interrupt service routine at this level cannot be interrupted in any arbitration mode. its mask can be both maskable (tli) or non-maskable (tlnm). 3.4 priority level arbitration the 3 bits of cpl (current priority level) in the central interrupt control register contain the pri- ority of the currently running program (cpu priori- ty). cpl is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware accord- ing to the selected arbitration mode. during every instruction, an arbitration phase takes place, during which, for every channel capa- ble of generating an interrupt, each priority level is compared to all the other requests (interrupts or dma). if the highest priority request is an interrupt, its prl value must be strictly lower (that is, higher pri- ority) than the cpl value stored in the cicr regis- ter (r230) in order to be acknowledged. the top level interrupt overrides every other priority. 3.4.1 priority level 7 (lowest) interrupt requests at prl level 7 cannot be ac- knowledged, as this prl value (the lowest possi- ble priority) cannot be strictly lower than the cpl value. this can be of use in a fully polled interrupt environment. 3.4.2 maximum depth of nesting no more than 8 routines can be nested. if an inter- rupt routine at level n is being serviced, no other interrupts located at level n can interrupt it. this guarantees a maximum number of 8 nested levels including the top level interrupt request. 3.4.3 simultaneous interrupts if two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every st9 version, selects the channel encsr bit 0 1 mode st9 compatible st9+ pushed/popped registers pc, flagr pc, flagr, csr max. code size for interrupt service routine 64kb within 1 segment no limit across segments 1
41/179 st92141 - interrupts priority level arbitration ( contd) with the highest position in the chain, as shown in table 11 . table 11. daisy chain priority 3.4.4 dynamic priority level modification the main program and routines can be specifically prioritized. since the cpl is represented by 3 bits in a read/write register, it is possible to modify dy- namically the current priority value during program execution. this means that a critical section can have a higher priority with respect to other inter- rupt requests. furthermore it is possible to priori- tize even the main program execution by modify- ing the cpl during its execution. see figure 16 figure 16. example of dynamic priority level modification in nested mode 3.5 arbitration modes the st9 provides two interrupt arbitration modes: concurrent mode and nested mode. concurrent mode is the standard interrupt arbitration mode. nested mode improves the effective interrupt re- sponse time when service routine nesting is re- quired, depending on the request priority levels. the iam control bit in the cicr register selects concurrent arbitration mode or nested arbitration mode. 3.5.1 concurrent mode this mode is selected when the iam bit is cleared (reset condition). the arbitration phase, performed during every instruction, selects the request with the highest priority level. the cpl value is not modified in this mode. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. end of interrupt routine the interrupt service routine must be ended with the iret instruction. the iret instruction exe- cutes the following operations: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C if encsr is reset, csr is used instead of isr. normal program execution thus resumes at the in- terrupted instruction. all pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). note : in concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the cpl. no trace is kept of its value during the isr. if other requests are issued during the inter- rupt service routine, once the global cicr.ien is re-enabled, they will be acknowledged regardless of the interrupt service routines priority. this may cause undesirable interrupt response sequences. highest position lowest position inta0 / watchdog timer inta1 / standard timer intb0 / extended function timer intc1 / spi intd0 / rccu intd1 / wkup mgt induction motor controller ad converter 6 5 4 7 priority level main cpl is set to 5 cpl=7 main int 6 cpl=6 int6 ei cpl is set to 7 cpl6 > cpl5: int6 pending interrupt 6 has priority level 6 by main program 1
42/179 st92141 - interrupts arbitration modes (contd) examples in the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. example 1 in the first example, (simplest case, figure 17 ) the ei instruction is not used within the interrupt serv- ice routines. this means that no new interrupt can be serviced in the middle of the current one. the interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes. figure 17. simple example of a sequence of interrupt requests with: - concurrent mode selected and - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 priority level of main int 5 int 2 int 3 int 4 main int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 interrupt request 1
43/179 st92141 - interrupts arbitration modes (contd) example 2 in the second example, (more complex, figure 18 ), each interrupt service routine sets interrupt enable with the ei instruction at the beginning of the routine. placed here, it minimizes response time for requests with a higher priority than the one being serviced. the level 2 interrupt routine (with the highest prior- ity) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be inter- rupted by the level 4 interrupt routine. when the level 4 interrupt routine is completed, the level 3 in- terrupt routine resumes and finally the level 2 inter- rupt routine. this results in the three interrupt serv- ice routines being executed in the opposite order of their priority. it is therefore recommended to avoid inserting the ei instruction in the interrupt service rou- tine in concurrent mode . use the ei instruc- tion only in nested mode. warning: if, in concurrent mode, interrupts are nested (by executing ei in an interrupt service routine), make sure that either encsr is set or csr=isr, otherwise the iret of the innermost in- terrupt will make the cpu use csr instead of isr before the outermost interrupt service routine is terminated, thus making the outermost routine fail. figure 18. complex example of a sequence of interrupt requests with: - concurrent mode selected - ien set to 1 during interrupt service routine execution 6 5 4 3 2 1 0 7 main int 5 int 2 int 3 int 4 int 5 int 4 int 3 int 2 cpl is set to 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 cpl = 7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 3 cpl = 7 cpl = 7 int 5 cpl = 7 main ei ei ei priority level of interrupt request ei 1
44/179 st92141 - interrupts arbitration modes (contd) 3.5.2 nested mode the difference between nested mode and con- current mode, lies in the modification of the cur- rent priority level (cpl) during interrupt process- ing. the arbitration phase is basically identical to con- current mode, however, once the request is ac- knowledged, the cpl is saved in the nested inter- rupt control register (nicr) by setting the nicr bit corresponding to the cpl value (i.e. if the cpl is 3, the bit 3 will be set). the cpl is then loaded with the priority of the re- quest just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being exe- cuted. start of interrupt routine the interrupt cycle performs the following steps: C all maskable interrupt requests are disabled by clearing cicr.ien. C cpl is saved in the special nicr stack to hold the priority level of the suspended routine. C priority level of the acknowledged routine is stored in cpl, so that the next request priority will be compared with the one of the routine cur- rently being serviced. C the pc low byte is pushed onto system stack. C the pc high byte is pushed onto system stack. C if encsr is set, csr is pushed onto system stack. C the flag register is pushed onto system stack. C the pc is loaded with the 16-bit vector stored in the vector table, pointed to by the ivr. C if encsr is set, csr is loaded with isr con- tents; otherwise isr is used in place of csr until iret instruction. figure 19. simple example of a sequence of interrupt requests with: - nested mode - ien unchanged by the interrupt routines 6 5 4 3 2 1 0 7 main int 2 int0 int4 int3 int2 cpl is set to 7 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 main int 3 cpl=3 int 6 cpl=6 int5 int 0 cpl=0 int6 int2 interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced next int 2 cpl=2 int 4 cpl=4 int 5 cpl=5 priority level of interrupt request 1
45/179 st92141 - interrupts arbitration modes (contd) end of interrupt routine the iret interrupt return instruction executes the following steps: C the flag register is popped from system stack. C if encsr is set, csr is popped from system stack. C the pc high byte is popped from system stack. C the pc low byte is popped from system stack. C all unmasked interrupts are enabled by setting the cicr.ien bit. C the priority level of the interrupted routine is popped from the special register (nicr) and copied into cpl. C if encsr is reset, csr is used instead of isr, unless the program returns to another nested routine. the suspended routine thus resumes at the inter- rupted instruction. figure 19 contains a simple example, showing that if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent. figure 20 contains a more complex example showing how nested mode allows nested interrupt processing (enabled inside the interrupt service routines using the ei instruction) according to their priority level. figure 20. complex example of a sequence of interrupt requests with: - nested mode - ien set to 1 during the interrupt routine execution int 2 int 3 cpl=3 int 0 cpl=0 int6 6 5 4 3 2 1 0 7 main int 5 int 4 int0 int4 int3 int2 cpl is set to 7 cpl=5 cpl=4 cpl=2 cpl=7 ei interrupt 2 has priority level 2 interrupt 3 has priority level 3 interrupt 4 has priority level 4 interrupt 5 has priority level 5 int 2 int 4 cpl=2 cpl=4 int 5 cpl=5 main ei ei int 2 cpl=2 int 6 cpl=6 int5 int2 ei interrupt 6 has priority level 6 interrupt 0 has priority level 0 cpl6 > cpl3: int6 pending cpl2 < cpl4: serviced just after ei priority level of interrupt request ei 1
46/179 st92141 - interrupts 3.6 external interrupts the standard st9 core contains 8 external inter- rupts sources grouped into four pairs. table 12. external interrupt channel grouping each source has a trigger control bit tea0,..ted1 (r242,eitr.0,..,7 page 0) to select triggering on the rising or falling edge of the external pin. if the trigger control bit is set to 1, the corresponding pending bit ipa0,..,ipd1 (r243,eipr.0,..,7 page 0) is set on the input pin rising edge, if it is cleared, the pending bit is set on the falling edge of the in- put pin. each source can be individually masked through the corresponding control bit ima0,..,imd1 (eimr.7,..,0). see figure 22 . the priority level of the external interrupt sources can be programmed among the eight priority lev- els with the control register eiplr (r245). the pri- ority level of each pair is software defined using the bits prl2, prl1. for each pair, the even channel (a0,b0,c0,d0) of the group has the even priority level and the odd channel (a1,b1,c1,d1) has the odd (lower) priority level. figure 21. priority level examples n figure 21 shows an example of priority levels. figure 22 gives an overview of the external inter- rupt control bits and vectors. C the source of the interrupt channel a0 can be selected between the external pin int0 (when ia0s = 1, the reset value) or the on-chip timer/ watchdog peripheral (when ia0s = 0). C the source of the interrupt channel d0 can be selected between the external pin int6 (when int_sel = 0) or the on-chip rccu. warning: when using channels shared by both external interrupts and peripherals, special care must be taken to configure their control registers for both peripherals and interrupts. table 13. multiplexed interrupt sources external interrupt channel none int6 intd1 intd0 none none intc1 intc0 none none intb1 intb0 none int0 inta1 inta0 channel internal interrupt source external interrupt source inta0 timer/watchdog int0 intd0 rccu int6 1001001 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a int.d1: int.c1: 001=1 int.d0: source priority priorit y source int.a0: 010=2 int.a1: 011=3 int.b1: 101=5 int.b0: 100=4 int.c0: 000=0 eiplr vr000151 0 100=4 101=5 1
47/179 st92141 - interrupts external interrupts (contd) figure 22. external interrupts control bits and vectors n n int a0 request vector priority level mask bit pending bit ima0 ipa0 v7 v6 v5 v4 0 0 0 0 0 1 ia0s watchdog/timer end of count int 0 pin int a1 request int b0 request int b1 request int c0 request int c1 request int d0 request ted0 int 6 pin int d1 request vector priority level mask bit pending bit ima1 ipa1 v7 v6 v5 v4 0 0 1 0 1 v7 v6 v5 v4 0 1 00 v7 v6 v5 v4 0 1 1 0 v7 v6 v5 v4 1 0 0 0 v7 v6 v5 v4 1 0 1 0 v7 v6 v5 v4 1 1 0 0 v7 v6 v5 v4 1 1 1 0 vector priority level vector priority level vector priority level vector priority level vector priority level vector priority level mask bit imb0 pending bit ipb0 pending bit ipb1 pending bit ipc0 pending bit ipc1 pending bit ipd0 pending bit ipd1 mask bit imb1 mask bit imc0 mask bit imc1 mask bit imd0 mask bit imd1 * shared channels, see warning * eftis eft interrupt spis spi interrupt 1 0 int_sel rccu interrupt 1 0 tea0 * 0 pl2a pl1a 1 pl2c pl1c 0 pl2b pl1b 0 pl2a pl1a 1 pl2b pl1b 0 pl2c pl1c 0 pl2d pl1d 1 pl2d pl1d 1 0 id1s wuimu interrupt not connected not connected not connected not connected not connected 1 ints stim interrupt 1 not connected 0 1
48/179 st92141 - interrupts 3.7 top level interrupt the top level interrupt channel can be assigned either to the external pin nmi or to the timer/ watchdog according to the status of the control bit eivr.tlis (r246.2, page 0). if this bit is high (the reset condition) the source is the external pin nmi. if it is low, the source is the timer/ watchdog end of count. when the source is the nmi external pin, the control bit eivr.tltev (r246.3; page 0) selects between the rising (if set) or falling (if reset) edge generating the interrupt request. when the selected event occurs, the cicr.tlip bit (r230.6) is set. depending on the mask situation, a top level interrupt request may be generated. two kinds of masks are available, a maskable mask and a non-maskable mask. the first mask is the cicr.tli bit (r230.5): it can be set or cleared to enable or disable respectively the top level inter- rupt request. if it is enabled, the global enable in- terrupt bit, cicr.ien (r230.4) must also be ena- bled in order to allow a top level request. the second mask nicr.tlnm (r247.7) is a set- only mask. once set, it enables the top level in- terrupt request independently of the value of cicr.ien and it cannot be cleared by the pro- gram. only the processor reset cycle can clear this bit. this does not prevent the user from ignor- ing some sources due to a change in tlis. the top level interrupt service routine cannot be interrupted by any other interrupt or dma request, in any arbitration mode, not even by a subsequent top level interrupt request. warning . the interrupt machine cycle of the top level interrupt does not clear the cicr.ien bit, and the corresponding iret does not set it. furthermore the tli never modifies the cpl bits and the nicr register. 3.8 on-chip peripheral interrupts the general structure of the peripheral interrupt unit is described here, however each on-chip pe- ripheral has its own specific interrupt unit contain- ing one or more interrupt channels, or dma chan- nels. please refer to the specific peripheral chap- ter for the description of its interrupt features and control registers. the on-chip peripheral interrupt channels provide the following control bits: C interrupt pending bit (ip). set by hardware when the trigger event occurs. can be set/ cleared by software to generate/cancel pending interrupts and give the status for interrupt polling. C interrupt mask bit (im). if im = 0, no interrupt request is generated. if im =1 an interrupt re- quest is generated whenever ip = 1 and cicr.ien = 1. C priority level (prl, 3 bits). these bits define the current priority level, prl=0: the highest pri- ority, prl=7: the lowest priority (the interrupt cannot be acknowledged) C interrupt vector register (ivr, up to 7 bits). the ivr points to the vector table which itself contains the interrupt routine start address. figure 23. top level interrupt structure n watchdog enable wden watchdog timer end of count nmi or tltev mux tlis tlip tlnm tli ien pending mask top level interrupt va00294 core reset request imc 1
49/179 st92141 - interrupts 3.9 nmi/wkp0 line management in the st92141, the non maskable interrupt (nmi) and the wake up 0 line (wkup0) functionalities are both physically mapped on the same i/o port pin p5.1 (refer to section 1.2). the nmi/wkup0 is a single alternate function in- put, associated with pin p5.1. it is input to the in- duction motor controller (imc) and the wake up management unit (wuimu). the imc controller processes the nmi input and generates the non maskable interrupt request to the cpu (refer to figure 24 and imc figure 71 ). figure 24. nmi/wkup0 line management nmi event handling to enable an nmi event on the nmi/wkup0 line, the following bits must be programmed: C tlnm bit in the nicr register, C tli and ien bits in the cicr register C nmi bit in the imcivr register C nmil bit in the pbr register C nmie bit in the pcr1 register an event on the nmi/wkup0 line is handled by the st92141 in the following way: C a nmi event is acknowledged in the cpu only when the internal clock intclk is running (i.e. when the st92141 is not in stop mode). C a nmi event is immediately acknowledged in the imc. the st92141 can be either in stop or in run mode (the nmi/wkup0 line is detected asynchronously). wake-up event handling to enable a wake-up event on the nmi/wkup0 line, the following bits must be programmed: C wumx bits in the wumrl register C wutx bits in the wutrl register an event on the nmi/wkup0 or the wkup[3:1] lines is handled by the st92141 in the following way: C a wake up event of one external line (out of the four available), is immediately acknowledged in the wuimu. the st92141 can be either in stop or in run mode (the nmi/wkup0 and wkup[3:1] lines are detected asynchronously). uh/ul/vh vl/wh/wl input buffer cpu wuimu output buffers p5.1 imc stop request to rccu nmi/wkup0 wkup0 nmi nmi to cpu 1
50/179 st92141 - interrupts nmi/wkp0 line management (contd) 3.9.1 nmi/wake-up event handling in run mode the four external lines wkup0/nmi, wkup1-3 can also be used when the device is in run mode. in addition, if the wkup0/nmi line is used and the nmi and wkup0 events are enabled by program- ming the cpu, imc and wuimu registers, a tran- sition on the input pin can generate the following events: C imc : the six output phases uh/ul/vh/vl/wh/ wl are released in high impedance. the nmi bit of the imcivr register is automatically set to 1. a non maskable interrupt request is then sent to the cpu. C cpu : the nmi pending bit of the cicr register is set and the corresponding nmi interrupt routine is immediately executed. note 1 : the nmi pending bits of the imcivr reg- ister must be cleared by software in the nmi rou- tine, whereas the nmi pending bit of the cicr register is cleared by hardware when nmi routine is acknowledged. note 2 : the external nmi/wkup0 event is flagged in the nmi pending bit of the imcivr register. the nmi routine must clear this bit. this operation must occur after disactivation of the nmi/wkup0 line (otherwise, the next nmi/wkup0 event will be lost, if the cpu is sensitive to a rising edge on the nmi input). the flexibility of the st9 also allows the use of the nmi/wkup0 line as a wake up function only or as a non maskable interrupt only. warning: 1. the nmi management implemented in the st92141 imposes the following constraints on the p5.3 (nmi/wkup0) i.o pin: C no glitches should occur on the pin to avoid un- intentional nmi/wake up requests. C a minimum pulse width is requested for the pin activation (refer to st92141 electrical specifica- tion). 2. the wkup0-3 management implemented in the st92141 imposes the following constraints on the p5.0 (wkup1), p5.2 (wkup0), p3.2 (wkup3) and p3.6 (wkup2): C no glitches should occur on wkup0-3 pins to avoid unintentional requests. 3.9.2 nmi/wake-up event handling in stop mode the st92141 enters stop mode by software writ- ing a special stop bit setting sequence in the wuctrl register of the wuimu. after entering stop mode, the device can be woken up by one of the four wake up external lines (refer to section 3.12 wake-up / interrupt lines manage- ment unit (wuimu) . in addition, if the wkup0/nmi line is used and the nmi and wkup0 events are enabled by program- ming the cpu, imc and wuimu registers, a tran- sition on the input pin can generate the following events: C imc : the six output phases uh/ul/vh/vl/wh/ wl are released in high impedance. the nmi bit of the imcivr register is automatically set to 1. a non maskable interrupt request is then sent to the cpu. C wuimu : the nmi/wkup0 activation wakes up the st92141 from stop mode, allowing the cpu to acknowledge the nmi request from imc C cpu : the nmi pending bit of the cicr register is set and the corresponding nmi interrupt routine is executed as soon as the st92141 is exited from stop mode. note : the nmi pending bits of the imcivr register must be cleared by software in the nmi routine, whereas the nmi pending bit of the cicr register is cleared by hardware when the nmi routine is ac- knowledged. 3.9.3 unused wake up management unit lines the wuimu can manage up to 16 external-inter- rupt/ wake up lines. usually, only a subset of these 16 lines is used. in the st92141, 4 lines out of 16 are available as external lines (wkup0/1/2/3) but the pending and mask bits of the unused lines (wkup4 to wkup 15) are also accessible by software (refer to sec- tion 3.12 wake-up / interrupt lines man- agement unit (wuimu) ). therefore, it is possi- ble to generate a software interrupt by disabling the mask and by setting the pending bit of an un- used channel. 1
51/179 st92141 - interrupts 3.10 interrupt response time the interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. one more cpuclk cycle is required when an interrupt is acknowledged. requests are sampled every 5 cpuclk cycles. if the interrupt request comes from an external pin, the trigger event must occur a minimum of one intclk cycle before the sampling time. when an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immedi- ately and the interrupt request is serviced; if not, the cpu waits until the current instruction is termi- nated and then services the request. instruction execution can normally be aborted provided no write operation has been performed. for an interrupt deriving from an external interrupt channel, the response time between a user event and the start of the interrupt service routine can range from a minimum of 26 clock cycles to a max- imum of 55 clock cycles (div instruction), 53 clock cycles (divws and mul instructions) or 49 for other instructions. for a non-maskable top level interrupt, the re- sponse time between a user event and the start of the interrupt service routine can range from a min- imum of 22 clock cycles to a maximum of 51 clock cycles (div instruction), 49 clock cycles (divws and mul instructions) or 45 for other instructions. in order to guarantee edge detection, input signals must be kept low/high for a minimum of one intclk cycle. an interrupt machine cycle requires a basic 18 in- ternal clock cycles (cpuclk), to which must be added a further 2 clock cycles if the stack is in the register file. 2 more clock cycles must further be added if the csr is pushed (encsr =1). the interrupt machine cycle duration forms part of the two examples of interrupt response time previ- ously quoted; it includes the time required to push values on the stack, as well as interrupt vector handling. in wait for interrupt mode, a further cycle is re- quired as wake-up delay. 1
52/179 st92141 - interrupts 3.11 interrupt registers central interrupt control register (cicr) r230 - read/write register group: system reset value: 1000 0111 (87h) bit 7 = gcen : global counter enable. this bit enables the 16-bit multifunction timer pe- ripheral. 0: mft disabled 1: mft enabled bit 6 = tlip : top level interrupt pending . this bit is set by hardware when top level inter- rupt (tli) trigger event occurs. it is cleared by hardware when a tli is acknowledged. it can also be set by software to implement a software tli. 0: no tli pending 1: tli pending bit 5 = tli : top level interrupt. this bit is set and cleared by software. 0: a top level interrupt is generated when tlip is set, only if tlnm=1 in the nicr register (inde- pendently of the value of the ien bit). 1: a top level interrupt request is generated when ien=1 and the tlip bit are set. bit 4 = ien : interrupt enable . this bit is cleared by the interrupt machine cycle (except for a tli). it is set by the iret instruction (except for a return from tli). it is set by the ei instruction. it is cleared by the di instruction. 0: maskable interrupts disabled 1: maskable interrupts enabled note: the ien bit can also be changed by soft- ware using any instruction that operates on regis- ter cicr, however in this case, take care to avoid spurious interrupts, since ien cannot be cleared in the middle of an interrupt arbitration. only modify the ien bit when interrupts are disabled or when no peripheral can generate interrupts. for exam- ple, if the state of ien is not known in advance, and its value must be restored from a previous push of cicr on the stack, use the sequence di; pop cicr to make sure that no interrupts are be- ing arbitrated when cicr is modified. bit 3 = iam : interrupt arbitration mode . this bit is set and cleared by software. 0: concurrent mode 1: nested mode bit 2:0 = cpl[2:0]: current priority level . these bits define the current priority level. cpl=0 is the highest priority. cpl=7 is the lowest priority. these bits may be modified directly by the interrupt hardware when nested interrupt mode is used. external interrupt trigger register (eitr) r242 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ted1 : intd1 trigger event bit 6 = ted0 : intd0 trigger event bit 5 = tec1 : intc1 trigger event bit 4 = tec0 : intc0 trigger event bit 3 = teb1 : intb1 trigger event bit 2 = teb0 : intb0 trigger event bit 1 = tea1 : inta1 trigger event bit 0 = tea0 : inta0 trigger event these bits are set and cleared by software. 0: select falling edge as interrupt trigger event 1: select rising edge as interrupt trigger event 70 gcen tlip tli ien iam cpl2 cpl1 cpl0 70 ted1 ted0 tec1 tec0 teb1 teb0 tea1 tea0 1
53/179 st92141 - interrupts interrupt registers (contd) external interrupt pending register (eipr) r243 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = ipd1 : intd1 interrupt pending bit bit 6 = ipd0 : intd0 interrupt pending bit bit 5 = ipc1 : intc1 interrupt pending bit bit 4 = ipc0 : intc0 interrupt pending bit bit 3 = ipb1 : intb1 interrupt pending bit bit 2 = ipb0 : intb0 interrupt pending bit bit 1 = ipa1 : inta1 interrupt pending bit bit 0 = ipa0 : inta0 interrupt pending bit these bits are set by hardware on occurrence of a trigger event (as specified in the eitr register) and are cleared by hardware on interrupt acknowl- edge. they can also be set by software to imple- ment a software interrupt. 0: no interrupt pending 1: interrupt pending external interrupt mask-bit register (eimr) r244 - read/write register page: 0 reset value: 0000 0000 (00h ) bit 7 = imd1 : intd1 interrupt mask bit 6 = imd0 : intd0 interrupt mask bit 5 = imc1 : intc1 interrupt mask bit 4 = imc0 : intc0 interrupt mask bit 3 = imb1 : intb1 interrupt mask bit 2 = imb0 : intb0 interrupt mask bit 1 = ima1 : inta1 interrupt mask bit 0 = ima0 : inta0 interrupt mask these bits are set and cleared by software. 0: interrupt masked 1: interrupt not masked (an interrupt is generated if the ipxx and ien bits = 1) external interrupt priority level register (eiplr) r245 - read/write register page: 0 reset value: 1111 1111 (ffh ) bit 7:6 = pl2d, pl1d: intd0, d1 priority level. bit 5:4 = pl2c, pl1c : intc0, c1 priority level. bit 3:2 = pl2b, pl1b : intb0, b1 priority level. bit 1:0 = pl2a, pl1a : inta0, a1 priority level. these bits are set and cleared by software. the priority is a three-bit value. the lsb is fixed by hardware at 0 for channels a0, b0, c0 and d0 and at 1 for channels a1, b1, c1 and d1. 70 ipd1 ipd0 ipc1 ipc0 ipb1 ipb0 ipa1 ipa0 70 imd1 imd0 imc1 imc0 imb1 imb0 ima1 ima0 70 pl2d pl1d pl2c pl1c pl2b pl1b pl2a pl1a pl2x pl1x hardware bit priority 00 0 1 0 (highest) 1 01 0 1 2 3 10 0 1 4 5 11 0 1 6 7 (lowest) 1
54/179 st92141 - interrupts interrupt registers (contd) external interrupt vector register (eivr ) r246 - read/write register page: 0 reset value: xxxx 0110b (x6h) bit 7:4 = v[7:4] : most significant nibble of external interrupt vector . these bits are not initialized by reset. for a repre- sentation of how the full vector is generated from v[7:4] and the selected external interrupt channel, refer to figure 22 . bit 3 = tltev : top level trigger event bit. this bit is set and cleared by software. 0: select falling edge as nmi trigger event 1: select rising edge as nmi trigger event bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source bit 0 = ewen : external wait enable. this bit is set and cleared by software. 0: waitn pin disabled 1: waitn pin enabled (to stretch the external memory access cycle). note: for more details on wait mode refer to the section describing the waitn pin in the external memory chapter. nested interrupt control (nicr) r247 - read/write register page: 0 reset value: 0000 0000 (00h) bit 7 = tlnm : top level not maskable . this bit is set by software and cleared only by a hardware reset. 0: top level interrupt maskable. a top level re- quest is generated if the ien, tli and tlip bits =1 1: top level interrupt not maskable. a top level request is generated if the tlip bit =1 bit 6:0 = hl[6:0] : hold level x these bits are set by hardware when, in nested mode, an interrupt service routine at level x is in- terrupted from a request with higher priority (other than the top level interrupt request). they are cleared by hardware at the iret execution when the routine at level x is recovered. 70 v7 v6 v5 v4 tltev tlis iaos ewen 70 tlnm hl6 hl5 hl4 hl3 hl2 hl1 hl0 1
55/179 st92141 - interrupts 3.12 wake-up / interrupt lines management unit (wuimu) 3.12.1 introduction the wake-up/interrupt management unit extends the number of external interrupt lines from 8 to 23 (depending on the number of external interrupt lines mapped on external pins of the device). it al- lows the source of the intd1 external interrupt channel to be used for up to 16 additional external wake-up/interrupt pins. these 16 wkup pins can be programmed as ex- ternal interrupt lines or as wake-up lines, able to exit the microcontroller from low power mode (stop mode) (see figure 25 ). 3.12.2 main features n supports up to 16 additional external wake-up or interrupt lines n wake-up lines can be used to wake-up the st9 from stop mode. n programmable selection of wake-up or interrupt n programmable wake-up trigger edge polarity n all wake-up lines maskable note: the number of available pins is device de- pendent. refer to the device pinout description. figure 25. wake-up lines / interrupt management unit block diagram wutrh wutrl wuprh wuprl wumrh wumrl triggering level registers pending request registers mask registers wkup[7:0] wkup[15:8] 10 set wuctrl sw setting wkup-int id1s stop reset to rccu - stop mode control to cpu intd1 - external interrupt channel note: reset signal on stop bit is stronger than the set signal int7 (not connected) 1
56/179 st92141 - interrupts wake-up / interrupt lines management unit (contd) 3.12.3 functional description 3.12.3.1 interrupt mode to configure the 16 wake-up lines as interrupt sources, use the following procedure: 1. configure the mask bits of the 16 wake-up lines (wumrl, wumrh). 2. configure the triggering edge registers of the wake-up lines (wutrl, wutrh). 3. set bit 7 of eimr (r244 page 0) and eitr (r242 page 0) registers of the cpu: so an interrupt coming from one of the 16 lines can be correctly acknowledged. 4. reset the wkup-int bit in the wuctrl regis- ter to disable wake-up mode. 5. set the id1s bit in the wuctrl register to dis- able the int7 external interrupt source and enable the 16 wake-up lines as external inter- rupt source lines. to return to standard mode (int7 external inter- rupt source enabled and 16 wake-up lines disa- bled) it is sufficient to reset the id1s bit. 3.12.3.2 wake-up mode selection to configure the 16 lines as wake-up sources, use the following procedure: 1. configure the mask bits of the 16 wake-up lines (wumrl, wumrh). 2. configure the triggering edge registers of the wake-up lines (wutrl, wutrh). 3. set, as for interrupt mode selection, bit 7 of eimr and eitr registers only if an interrupt routine is to be executed after a wake-up event. otherwise, if the wake-up event only restarts the execution of the code from where it was stopped, the intd1 interrupt channel must be masked or the external source must be selected by resetting the id1s bit. 4. since the rccu can generate an interrupt request when exiting from stop mode, take care to mask it even if the wake-up event is only to restart code execution. 5. set the wkup-int bit in the wuctrl register to select wake-up mode. 6. set the id1s bit in the wuctrl register to dis- able the int7 external interrupt source and enable the 16 wake-up lines as external inter- rupt source lines. this is not mandatory if the wake-up event does not require an interrupt response. 7. write the sequence 1,0,1 to the stop bit of the wuctrl register with three consecutive write operations. this is the stop bit setting sequence. to detect if stop mode was entered or not, im- mediately after the stop bit setting sequence, poll the rccu ex_stp bit (r242.7, page 55) and the stop bit itself. 3.12.3.3 stop mode entry conditions assuming the st9 is in run mode: during the stop bit setting sequence the following cases may occur: case 1: wrong stop bit setting sequence this can happen if an interrupt/dma request is ac- knowledged during the stop bit setting se- quence. in this case polling the stop and ex_stp bits will give: stop = 0, ex_stp = 0 this means that the st9 did not enter stop mode due to a bad stop bit setting sequence: the user must retry the sequence. case 2: correct stop bit setting sequence in this case the st9 enters stop mode. to exit stop mode, a wake-up interrupt must be acknowledged. that implies: stop = 0, ex_stp = 1 this means that the st9 entered and exited stop mode due to an external wake-up line event. case 3: a wake-up event on the external wake- up lines occurs during the stop bit setting se- quence there are two possible cases: 1. interrupt requests to the cpu are disabled: in this case the st9 will not enter stop mode, no interrupt service routine will be executed and the program execution continues from the instruction following the stop bit setting sequence. the status of stop and ex_stp bits will be again: stop = 0, ex_stp = 0 the application can determine why the st9 did not enter stop mode by polling the pending bits of the external lines (at least one must be at 1). 1
57/179 st92141 - interrupts wake-up / interrupt lines management unit (contd) 2. interrupt requests to cpu are enabled: in this case the st9 will not enter stop mode and the interrupt service routine will be executed. the status of stop and ex_stp bits will be again: stop = 0, ex_stp = 0 the interrupt service routine can determine why the st9 did not enter stop mode by polling the pending bits of the external lines (at least one must be at 1). if the mcu really exits from stop mode, the rccu ex_stp bit is still set and must be reset by software. otherwise, if an interrupt/dma request was acknowledged during the stop bit setting se- quence, the rccu ex_stp bit is reset. this means that the mcu has filtered the stop mode entry request. the wkup-int bit can be used by an interrupt routine to detect and to distinguish events coming from interrupt mode or from wake-up mode, allow- ing the code to execute different procedures. to exit stop mode, it is sufficient that one of the 16 wake-up lines (not masked) generates an event: the clock restarts after the delay needed for the oscillator to restart. note: after exiting from stop mode, the software can successfully reset the pending bits (edge sen- sitive), even though the corresponding wake-up line is still active (high or low, depending on the trigger event register programming); the user must poll the external pin status to detect and dis- tinguish a short event from a long one (for example keyboard input with keystrokes of varying length). 3.12.4 programming considerations the following paragraphs give some guidelines for designing an application program. 3.12.4.1 procedure for entering/exiting stop mode 1. program the polarity of the trigger event of external wake-up lines by writing registers wutrh and wutrl. 2. check that at least one mask bit (registers wumrh, wumrl) is equal to 1 (so at least one external wake-up line is not masked). 3. reset at least the unmasked pending bits: this allows a rising edge to be generated on the intd1 channel when the trigger event occurs (an interrupt on channel intd1 is recognized when a rising edge occurs). 4. select the interrupt source of the intd1 chan- nel (see description of id1s bit in the wuctrl register) and set the wkup-int bit. 5. to generate an interrupt on channel intd1, bits eitr.1 (r242.7, page 0) and eimr.1 (r244.7, page 0) must be set and bit eipr.7 must be reset. bits 7 and 6 of register r245, page 0 must be written with the desired priority level for interrupt channel intd1. 6. reset the stop bit in register wuctrl and the ex_stp bit in the clk_flag register (r242.7, page 55). refer to the rccu chapter. 7. to enter stop mode, write the sequence 1, 0, 1 to the stop bit in the wuctrl register with three consecutive write operations. 8. the code to be executed just after the stop sequence must check the status of the stop and rccu ex_stp bits to determine if the st9 entered stop mode or not (see wake-up mode selection on page 56. for details). if the st9 did not enter in stop mode it is necessary to reloop the procedure from the beginning, oth- erwise the procedure continues from next point. 9. poll the wake-up pending bits to determine which wake-up line caused the exit from stop mode. 10.clear the wake-up pending bit that was set. 1
58/179 st92141 - interrupts wake-up / interrupt lines management unit (contd) 3.12.4.2 simultaneous setting of pending bits it is possible that several simultaneous events set different pending bits. in order to accept subse- quent events on external wake-up/interrupt lines, it is necessary to clear at least one pending bit: this operation allows a rising edge to be generated on the intd1 line (if there is at least one more pend- ing bit set and not masked) and so to set eipr.7 bit again. a further interrupt on channel intd1 will be serviced depending on the status of bit eimr.7. two possible situations may arise: 1. the user chooses to reset all pending bits: no further interrupt requests will be generated on channel intd1. in this case the user has to: C reset eimr.7 bit (to avoid generating a spuri- ous interrupt request during the next reset op- eration on the wuprh register) C reset wuprh register using a read-modify- write instruction (and, bres, band) C clear the eipr.7 bit C reset the wuprl register using a read-mod- ify-write instruction (and, bres, band) 2. the user chooses to keep at least one pending bit active: at least one additional interrupt request will be generated on the intd1 chan- nel. in this case the user has to reset the desired pending bits with a read-modify-write instruction (and, bres, band). this operation will generate a rising edge on the intd1 chan- nel and the eipr.7 bit will be set again. an interrupt on the intd1 channel will be serviced depending on the status of eimr.7 bit. 1
59/179 st92141 - interrupts wake-up / interrupt lines management unit (contd) 3.12.5 register description wake-up control register ( wuctrl) r249 - read/write register page: 57 reset value: 0000 0000 (00h) bit 2 = stop: stop bit. to enter stop mode, write the sequence 1,0,1 to this bit with three consecutive write operations . when a correct sequence is recognized, the stop bit is set and the rccu puts the mcu in stop mode. the software sequence succeeds only if the following conditions are true: C the wkup-int bit is 1, C all unmasked pending bits are reset, C at least one mask bit is equal to 1 (at least one external wake-up line is not masked). otherwise the mcu cannot enter stop mode, the program code continues executing and the stop bit remains cleared. the bit is reset by hardware if, while the mcu is in stop mode, a wake-up interrupt comes from any of the unmasked wake-up lines. the stop bit is at 1 in the two following cases (see wake-up mode selection on page 56. for details): C after the first write instruction of the sequence (a 1 is written to the stop bit) C at the end of a successful sequence (i.e. after the third write instruction of the sequence) warning : writing the sequence 1,0,1 to the stop bit will enter stop mode only if no other register write instructions are executed during the sequence. if interrupt or dma requests (which al- ways perform register write operations) are ac- knowledged during the sequence, the st9 will not enter stop mode: the user must re-enter the se- quence to set the stop bit. warning : whenever a stop request is issued to the mcu, a few clock cycles are needed to enter stop mode (see rccu chapter for further de- tails). hence the execution of the instruction fol- lowing the stop bit setting sequence might start before entering stop mode: if such instruction performs a register write operation, the st9 will not enter in stop mode. in order to avoid to exe- cute register write instructions after a correct stop bit setting sequence and before entering the stop mode, it is mandatory to execute 3 nop instructions after the stop bit setting sequence. bit 1 = id1s: interrupt channel intd1 source. this bit is set and cleared by software. 0: int7 external interrupt source selected, exclud- ing wake-up line interrupt requests 1: the 16 external wake-up lines enabled as inter- rupt sources, replacing the int7 external pin function warning: to avoid spurious interrupt requests on the intd1 channel due to changing the inter- rupt source, do the following before modifying the id1s bit: 1. mask the intd1 interrupt channel (bit 7 of reg- ister eimr - r244, page 0 - reset to 0). 2. program the id1s bit as needed. 3. clear the ipd1 interrupt pending bit (bit 7 of register eipr - r243, page 0). 4. remove the mask on intd1 (bit eimr.7=1). bit 0 = wkup-int: wakeup interrupt. this bit is set and cleared by software. 0: the 16 external wakeup lines can be used to generate interrupt requests 1: the 16 external wake-up lines to work as wake- up sources for exiting from stop mode 70 -----stopid1swkup-int 1
60/179 st92141 - interrupts wake-up / interrupt lines management unit (contd) wake-up mask register high ( wumrh) r250 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wum[15:8]: wake-up mask bits. if wumx is set, an interrupt on channel intd1 and/or a wake-up event (depending on id1s and wkup-int bits) are generated if the correspond- ing wupx pending bit is set. more precisely, if wumx=1 and wupx=1 then: C if id1s=1 and wkup-int=1 then an interrupt on channel intd1 and a wake-up event are gener- ated. C if id1s=1 and wkup-int=0 only an interrupt on channel intd1 is generated. C if id1s=0 and wkup-int=1 only a wake-up event is generated. C if id1s=0 and wkup-int=0 neither interrupts on channel intd1 nor wake-up events are gen- erated. interrupt requests on channel intd1 may be generated only from external interrupt source int7. if wumx is reset, no wake-up events can be gen- erated. interrupt requests on channel intd1 may be generated only from external interrupt source int7 (resetting id1s bit to 0). wake-up mask register low ( wumrl) r251 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wum[7:0]: wake-up mask bits. if wumx is set, an interrupt on channel intd1 and/or a wake-up event (depending on id1s and wkup-int bits) are generated if the correspond- ing wupx pending bit is set. more precisely, if wumx=1 and wupx=1 then: C if id1s=1 and wkup-int=1 then an interrupt on channel intd1 and a wake-up event are gener- ated. C if id1s=1 and wkup-int=0 only an interrupt on channel intd1 is generated. C if id1s=0 and wkup-int=1 only a wake-up event is generated. C if id1s=0 and wkup-int=0 neither interrupts on channel intd1 nor wake-up events are gen- erated. interrupt requests on channel intd1 may be generated only from external interrupt source int7. if wumx is reset, no wake-up events can be gen- erated. interrupt requests on channel intd1 may be generated only from external interrupt source int7 (resetting id1s bit to 0). 70 wum15 wum14 wum13 wum12 wum11 wum10 wum9 wum8 70 wum7 wum6 wum5 wum4 wum3 wum2 wum1 wum0 1
61/179 st92141 - interrupts wake-up / interrupt lines management unit (contd) wake-up trigger register high ( wutrh) r252 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wut[15:8]: wake-up trigger polarity bits these bits are set and cleared by software. 0: the corresponding wupx pending bit will be set on the falling edge of the input wake-up line. 1: the corresponding wupx pending bit will be set on the rising edge of the input wake-up line. wake-up trigger register low ( wutrl) r253 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wut[7:0]: wake-up trigger polarity bits these bits are set and cleared by software. 0: the corresponding wupx pending bit will be set on the falling edge of the input wake-up line. 1: the corresponding wupx pending bit will be set on the rising edge of the input wake-up line. warning 1. as the external wake-up lines are edge trig- gered, no glitches must be generated on these lines. 2. if either a rising or a falling edge on the external wake-up lines occurs while writing the wutrh or wutrl registers, the pending bit will not be set. wake-up pending register high ( wuprh) r254 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wup[15:8]: wake-up pending bits these bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. they must be cleared by software. they can be set by software to implement a software inter- rupt. 0: no wake-up trigger event occurred 1: wake-up trigger event occurred wake-up pending register low ( wuprl) r255 - read/write register page: 57 reset value: 0000 0000 (00h) bit 7:0 = wup[7:0]: wake-up pending bits these bits are set by hardware on occurrence of the trigger event on the corresponding wake-up line. they must be cleared by software. they can be set by software to implement a software inter- rupt. 0: no wake-up trigger event occurred 1: wake-up trigger event occurred note: to avoid losing a trigger event while clear- ing the pending bits, it is recommended to use read-modify-write instructions (and, bres, band) to clear them. 70 wut15 wut14 wut13 wut12 wut11 wut10 wut9 wut8 70 wut7 wut6 wut5 wut4 wut3 wut2 wut1 wut0 70 wup15 wup14 wup13 wup12 wup11 wup10 wup9 wup8 70 wup7 wup6 wup5 wup4 wup3 wup2 wup1 wup0 1
62/179 st92141 - em configuration registers (em) 4 em configuration registers (em) in st9 devices with external memory, the em reg- isters (external memory registers) are used to configure the external memory interface. in the st92141, only the bsz, encsr and dprem bits must be programmed. all other bits in these regis- ters must be left at their reset values. em register 1 (emr1) r245 - read/write register page: 21 reset value: 1000 0000 (80h) bit 7:2 = reserved. bit 1 = bsz : buffer size. 0: i/o ports p3.6, p3.5, p5.0, p5.2 use output buff- ers with standard current capability (less noisy). 1: i/o ports p3.6, p3.5, p5.0, p5.2 use output buff- ers with high current capability (more noisy) bit 0 = reserved. em register 2 (emr2) r246 - read/write register page: 21 reset value: 0000 1111 (0fh) bit 7 = reserved, keep in reset state. bit 6 = encsr : enable code segment register. this bit is set and cleared by software. it affects the st9 cpu behaviour whenever an interrupt re- quest is issued. 0: the cpu works in original st9 compatibility mode. for the duration of the interrupt service routine, isr is used instead of csr, and the in- terrupt stack frame is identical to that of the orig- inal st9: only the pc and flags are pushed. this avoids saving the csr on the stack in the event of an interrupt, thus ensuring a faster in- terrupt response time. the drawback is that it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the csr, which, in this case, is not used (isr is used instead). the code segment size for all interrupt service rou- tines is thus limited to 64k bytes. 1: isr is only used to point to the interrupt vector table and to initialize the csr at the beginning of the interrupt service routine: the old csr is pushed onto the stack together with the pc and flags, and csr is then loaded with the contents of isr. in this case, iret will also restore csr from the stack. this approach allows interrupt service routines to access the entire 4 mbytes of address space; the drawback is that the inter- rupt response time is slightly increased, be- cause of the need to also save csr on the stack. full compatibility with the original st9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. bit 5 = dprrem : data page registers remapping 0: the locations of the four mmu (memory man- agement unit) data page registers (dpr0, dpr1, dpr2 and dpr3) are in page 21. 1: the four mmu data page registers are swapped with that of the data registers of ports 0-3. refer to figure 11 bit 4:0 = reserved, keep in reset state. 70 100000bsz0 70 0encsrdprem01111 1
63/179 st92141 - reset and clock control unit (rccu) 5 reset and clock control unit (rccu) 5.1 introduction the reset and clock control unit (rccu) com- prises two distinct sections: C the clock control unit, which generates and manages the internal clock signals. C the reset/stop manager, which detects and flags hardware, software and watchdog gener- ated resets. in stop mode and halt mode, all oscillators are fro- zen in order to achieve the lowest possible power consumption. entering and exiting stop mode is controlled by the wuimu. halt mode is entered by executing the halt in- struction. halt mode can only be exited by a reset event. 5.2 clock control unit the clock control unit generates the internal clocks for the cpu core (cpuclk) and for the on- chip peripherals (intclk). the clock control unit may be driven by an external crystal circuit, con- nected to the oscin and oscout pins, or by an external pulse generator, connected to oscin (see figure 34 and figure 36 ). if present, another clock source named ck_af can be provided to the system. depending on the device, it can be a periodic signal applied to the ck_af pin or a sig- nal generated internally by the mcu (rc oscilla- tor). 5.2.1 clock control unit overview as shown in figure 26 , a programmable divider can divide the clock1 input clock signal by two. the resulting signal, clock2, is the reference in- put clock to the programmable phase locked loop frequency multiplier, which is capable of mul- tiplying the clock frequency by a factor of 6, 8, 10 or 14; the multiplied clock is then divided by a pro- grammable divider, by a factor of 1 to 7. by this means, the st9 can operate with cheaper, medi- um frequency (3-5 mhz) crystals, while still provid- ing a high frequency internal clock for maximum system performance; the range of available multi- plication and division factors allow a great number of operating clock frequencies to be derived from a single crystal frequency. the undivided pll clock is also available for special purposes (high-speed peripheral). for low power operation, especially in wait for in- terrupt mode, the clock multiplier unit may be turned off, whereupon the output clock signal may be programmed as clock2 divided by 16. fur- thermore, during the execution of a wfi in low power mode, the ck_af clock is automatically di- vided by 16 for further consumption reduction. (for the selection of this signal refer to the description the ck_af clock source in the following sections of this chapter). the internal system clock, intclk, is routed to all on-chip peripherals, as well as to the programma- ble clock prescaler unit which generates the clock for the cpu core (cpuclk). the clock prescaler is programmable and can slow the cpu clock by a factor of up to 8, allowing the programmer to reduce cpu processing speed, and thus power consumption, while maintaining a high speed clock to the peripherals. this is partic- ularly useful when little actual processing is being done by the cpu and the peripherals are doing most of the work. figure 26. clock control unit simplified block diagram quartz ck_af 1/16 1/2 oscillator pin clock2 clock1 ck_af pll clock multiplier cpu clock prescaler to cpu core to peripherals cpuclk intclk unit /divider 1/16 1
64/179 st92141 - reset and clock control unit (rccu) figure 27. st92141 clock distribution diagram (settings given for 5mhz crystal & 25mhz lnternal clock) 5 mhz pll 1/16 x 1/2 div2=1 1 oscillator mx1=0 mx0=0 csu_cksel=1 10 xt_div16=1 01 0 1 0 1 rccu 25 mhz intclk clock2 3-bit prescaler cpu imc 16-bit down counter 1/4 wdg cpuclk embedded memory ram eprom/fastrom stim 1...8 a/d 8-bit prescaler 1...256 p5.7 quartz dx2=0 dx1=0 dx0=0 01 1/16 ck_af pin 1 0 wfi and lpowfi=1 and wfi_cksel = 1 ck_af and wfi_cksel=1 or ckaf_sel=1 and lpowfi=1 wfi 1/4 conversion time n x 138 x intclk 3-bit prescaler 1...8 baud rate generator 1/n n=2,4,16,32 sck master sck slave (max intclk/2) spi logic 1/2 eft 1/n 16-bit up counter extclkx (max intclk/4) n=2,4,8 8-bit prescaler 1/2 16-bit down counter 8-bit prescaler 1...256 10-bit pwm 12-bit prescaler counter /otp n=1,4,6,8,10,12,14,16 1/n 1
65/179 st92141 - reset and clock control unit (rccu) 5.3 clock management the various programmable features and operating modes of the ccu are handled by four registers: C moder (mode register) this is a system register (r235, group e). the input clock divide-by-two and the cpu clock prescaler factors are handled by this register. C clkctl (clock control register) this is a paged register (r240, page 55). the low power modes and the interpretation of the halt instruction are handled by this register. C clk_flag (clock flag register) this is a paged register (r242, page 55). this register contains various status flags, as well as control bits for clock selection. C pllconf (pll configuration register) this is a paged register (r246, page 55). the pll multiplication and division factors are programmed in this register. figure 28. clock control unit programming quartz pll 1/16 x 1/2 div2 ckaf_sel 1/n oscillator mx(1:0) 0 1 0 1 0 1 ckaf_st csu_cksel 6/8/10/14 1 0 xt_div16 dx(2:0) clock2 clock1 (moder) (clk_flag) (clkctl) (pllconf) (clk_flag) ck_af intclk to peripherals and cpu clock prescaler xtstop (clk_flag) wait for interrupt and low power modes: lpowfi (clkctl) selects low power operation automatically on entering wfi mode. wfi_cksel (clkctl) selects the ck_af clock automatically, if present, on entering wfi mode. xtstop (clk_flag) automatically stops the xtal oscillator when the ck_af clock is present and selected. 1/16 ck_af pin wfi and lpowfi=1 and wfi_cksel = 1 0 1 1
66/179 st92141 - reset and clock control unit (rccu) clock management (contd) 5.3.1 pll clock multiplier programming the clock1 signal generated by the oscillator drives a programmable divide-by-two circuit. if the div2 control bit in moder is set (reset condi- tion), clock2, is equal to clock1 divided by two; if div2 is reset, clock2 is identical to clock1. since the input clock to the clock multi- plier circuit requires a 50% duty cycle for correct pll operation, the divide by two circuit should be enabled when a crystal oscillator is used, or when the external clock generator does not provide a 50% duty cycle. in practice, the divide-by-two is virtually always used in order to ensure a 50% duty cycle signal to the pll multiplier circuit. a clock1 signal with a semiperiod (high or low) shorter than 40ns is forbidden if the divider by two is disabled. when the pll is active, it multiplies clock2 by 6, 8, 10 or 14, depending on the status of the mx0 -1 bits in pllconf. the multiplied clock is then di- vided by a factor in the range 1 to 7, determined by the status of the dx0-2 bits; when these bits are programmed to 111, the pll is switched off. following a reset phase, programming bits dx0-2 to a value different from 111 will turn the pll on. after allowing a stabilisation period for the pll, setting the csu_cksel bit in the clk_flag register selects the multiplier clock this peripheral contains a lock-in logic that verifies if the pll is locked to the clock2 frequency. the bit lock in clk_flag register becomes 1 when this event occurs. the maximum frequency allowed for intclk is 25mhz for 5v operation, and 12mhz for 3v opera- tion. care is required, when programming the pll multiplier and divider factors, not to exceed the maximum permissible operating frequency for intclk, according to supply voltage. the st9 being a static machine, there is no lower limit for intclk. however, below 1mhz, a/d con- verter precision (if present) decreases. 5.3.2 cpu clock prescaling the system clock, intclk, which may be the out- put of the pll clock multiplier, clock2, clock2/ 16 or ck_af, drives a programmable prescaler which generates the basic time base, cpuclk, for the instruction executer of the st9 cpu core. this allows the user to slow down program execu- tion during non processor intensive routines, thus reducing power dissipation. the internal peripherals are not affected by the cpuclk prescaler and continue to operate at the full intclk frequency. this is particularly useful when little processing is being done and the pe- ripherals are doing most of the work. the prescaler divides the input clock by the value programmed in the control bits prs2,1,0 in the moder register. if the prescaler value is zero, no prescaling takes place, thus cpuclk has the same period and phase as intclk. if the value is different from 0, the prescaling is equal to the val- ue plus one, ranging thus from two (prs2,1,0 = 1) to eight (prs2,1,0 = 7). the clock generated is shown in figure 29 , and it will be noted that the prescaling of the clock does not preserve the 50% duty cycle, since the high level is stretched to replace the missing cycles. this is analogous to the introduction of wait cycles for access to external memory. when external memory wait or bus request events occur, cpu- clk is stretched at the high level for the whole pe- riod required by the function. figure 29. cpu clock prescaling 5.3.3 peripheral clock the system clock, intclk, which may be the out- put of the pll clock multiplier, clock2, clock2/ 16 or ck_af, is also routed to all st9 on-chip pe- ripherals and acts as the central timebase for all timing functions. intclk cpuclk va00260 000 001 010 011 100 101 110 111 prs value 1
67/179 st92141 - reset and clock control unit (rccu) clock management (contd) 5.3.4 low power modes the user can select an automatic slowdown of clock frequency during wait for interrupt opera- tion, thus idling in low power mode while waiting for an interrupt. in wfi operation the clock to the cpu core (cpuclk) is stopped, thus suspending program execution, while the clock to the peripher- als (intclk) may be programmed as described in the following paragraphs. an example of low power operation in wfi is illustrated in figure 30 . if low power operation during wfi is disabled (lpowfi bit = 0 in the clkctl register), the cpu clk is stopped but intclk is unchanged. if low power operation during wait for interrupt is enabled (lpowfi bit = 1 in the clkctl register), as soon as the cpu executes the wfi instruction, the pll is turned off and the system clock will be forced to clock2 divided by 16, or to the external low frequency clock, ck_af divided by 16 if this has been selected by setting wfi_cksel, and providing ckaf_st is set, thus indicating that the external clock is selected and actually present on the ck_af pin. the division by 16 is only selected by hardware after entering low power wfi mode. if the external clock source is used, the crystal os- cillator may be stopped by setting the xtstop bit, providing that the ck_af clock is present and se- lected, indicated by ckaf_st being set. the crys- tal oscillator will be stopped automatically on en- tering wfi if the wfi_cksel bit has been set. it should be noted that selecting a non-existent ck_af clock source is impossible, since such a selection requires that the auxiliary clock source be actually present and selected. in no event can a non-existent clock source be selected inadvert- ently. it is up to the user program to switch back to a fast- er clock on the occurrence of an interrupt, taking care to respect the oscillator and pll stabilisation delays, as appropriate.it should be noted that any of the low power modes may also be selected ex- plicitly by the user program even when not in wait for interrupt mode, by setting the appropriate bits. 5.3.5 interrupt generation system clock selection modifies the clkctl and clk_flag registers. the clock control unit generates an external inter- rupt request when ck_af and clock2/16 are selected or deselected as system clock source, as well as when the system clock restarts after a stop request (when the stop mode feature is availa- ble on the specific device). this interrupt can be masked by resetting the int_sel bit in the clkctl register. in the rccu the interrupt is generated with a high to low transition (see inter- rupt and dma chapters for further information). table 14. summary of operating modes using main crystal controlled oscillator mode intclk cpuclk div2 prs0-2 csu_cksel mx0-1 dx2-0 lpowfi xt_div16 pll x by 14 xtal/2 x (14/d) intclk/n 1 n-1 1 1 0 d-1 x 1 pll x by 10 xtal/2 x (10/d) intclk/n 1 n-1 1 0 0 d-1 x 1 pll x by 8 xtal/2 x (8/d) intclk/n 1 n-1 1 1 1 d-1 x 1 pll x by 6 xtal/2 x (6/d) intclk/n 1 n-1 1 0 1 d-1 x 1 slow 1 xtal/2 intclk/n 1 n-1 x x 111 x 1 slow 2 xtal/32 intclk/n 1 n-1 x x x x 0 wait for interrupt if lpowfi=0, no changes occur on intclk, but cpuclk is stopped anyway. low power wait for interrupt xtal/32 stop 1 x x x x 1 1 reset xtal/2 intclk 1 0 0 00 111 0 1 example xtal=4.4 mhz 2.2*10/2 = 11mhz 11mhz 1 0 1 00 001 x 1 1
68/179 st92141 - reset and clock control unit (rccu) figure 30. example of low power mode programming begin wfi_cksel ? 1 wfi status users program lpowfi ? 1 users program wfi end program flow comments system clock frequency interrupt quartz divided by 2 pll multiply factor multiplier dividers factor set wait for the ck_af clock selected when wfi wait for interrupt no code is executed until interrupt served fixed to 10. to 1, and pll turned on an interrupt is requested low power mode enabled main code execution continued 2.5 mhz 25 mhz 2.5 mhz 25 mhz ** t 2 = quartz oscillator start-up time * t 1 = pll lock-in time t 1 * t 2 ** t 1 * f q =5 mhz, v cc =5 v and t=25c ck_af/16 wait dx2-0 ? 000 xtal is selected to restart the pll quickly csu_cksel 1 pll is system clock source csu_cksel<- 1 while the ck_af is the system clock ckaf_sel <- 0 the system ck switches to xtal the pll is locked and becomes the system clock xtstop ? 0 to restart xtal and pll to stop pll and xtal when a wfi occurs xtstop ? 1 pll locking set up after reset phase: div2 = 1 xtstop = 0 mx(1:0) = 00 csu_cksel = 0 interrupt wait routine (lock->1) ck_af 1
69/179 st92141 - reset and clock control unit (rccu) 5.4 clock control registers mode register (moder) r235 - read/write system register reset value: 1110 0000 (e0h) *note : this register contains bits which relate to other functions; these are described in the chapter dealing with device architecture. only those bits relating to clock functions are described here. bit 5 = div2 : oscin divided by 2 . this bit controls the divide by 2 circuit which oper- ates on the oscin clock. 0: no division of the oscin clock 1: oscin clock is internally divided by 2 bit 4:2 = prs[2:0] : clock prescaling . these bits define the prescaler value used to pres- cale cpuclk from intclk. when these three bits are reset, the cpuclk is not prescaled, and is equal to intclk; in all other cases, the internal clock is prescaled by the value of these three bits plus one. clock control register (clkctl) r240 - read write register page: 55 reset value: 0000 0000 (00h) bit 7 = int_sel : interrupt selection . 0: select the external interrupt pin as interrupt source (reset state) 1: select the internal rccu interrupt (see section 5.3.5) bit 4:6 = reserved. must be kept reset for normal operation. bit 3 = sresen : software reset enable. 0: the halt instruction turns off the quartz, the pll and the ccu 1: a reset is generated when halt is executed bit 2 = ckaf_sel : alternate function clock se- lect. 0: ck_af clock not selected 1: select ck_af clock note: to check if the selection has actually oc- curred, check that ckaf_st is set. if no clock is present on the ck_af pin, the selection will not occur. bit 1 = wfi_cksel : wfi clock select . this bit selects the clock used during low power wfi mode if lpowfi = 1. 0: intclk during wfi is clock2/16 1: intclk during wfi is ck_af, further divided by 16, providing it is present. in effect this bit sets ckaf_sel in wfi mode warning : when the ck_af is selected as low power wfi clock but the xtal is not turned off (r242.4 = 0), after exiting from the wfi, ck_af will be still selected as system clock. in this case, reset the r240.2 bit to switch back to the xt. bit 0 = lpowfi : low power mode during wait for interrupt . 0: low power mode during wfi disabled. when wfi is executed, the cpuclk is stopped and intclk is unchanged 1: the st9 enters low power mode when the wfi instruction is executed. the clock during this state depends on wfi_cksel 70 - - div2 prs2 prs1 prs0 - - 70 int_sel - - - sresen ckaf_sel wfi_cksel lpowfi 1
70/179 st92141 - reset and clock control unit (rccu) clock control registers (contd) clock flag register (clk_flag) r242 -read/write register page: 55 reset value: 0100 1000 after a watchdog reset reset value: 0010 1000 after a software reset reset value: 0000 1000 after a power-on reset warning : if this register is accessed with a logi- cal instruction, such as and or or, some bits may not be set as expected. warning: if you select the ck_af as system clock and turn off the oscillator (bits r240.2 and r242.4 at 1), and then switch back to the xt clock by resetting the r240.2 bit, you must wait for the oscillator to restart correctly. bit 7 = ex_stp : stop mode flag this bit is set by hardware and cleared by soft- ware. 0: no stop condition occurred 1: stop condition occurred bit 6 = wdgres : watchdog reset flag. this bit is read only. 0: no watchdog reset occurred 1: watchdog reset occurred bit 5 = softres : software reset flag. this bit is read only. 0: no software reset occurred 1: software reset occurred (halt instruction) bit 4 = xtstop : oscillator stop enable. 0: xtal oscillator stop disabled 1: the xtal oscillator will be stopped as soon as the ck_af clock is present and selected, whether this is done explicitly by the user pro- gram, or as a result of wfi, if wfi_cksel has previously been set to select the ck_af clock during wfi. warning: when the program writes 1 to the xtstop bit, it will still be read as 0 and is only set when the ck_af clock is running (ckaf_st=1). take care, as any operation such as a subsequent and with `1' or an or with `0' to the xtstop bit will reset it and the oscillator will not be stopped even if ckaf_st is subsequently set. bit 3 = xt_div16 : clock/16 selection this bit is set and cleared by software. an interrupt is generated when the bit is toggled. 0: clock2/16 is selected and the pll is off 1: the input is clock2 (or the pll output de- pending on the value of csu_cksel) warning: after this bit is modified from 0 to 1, take care that the pll lock-in time has elapsed be- fore setting the csu_cksel bit. bit 2 = ckaf_st : (read only) if set, indicates that the alternate function clock has been selected. if no clock signal is present on the ck_af pin, the selection will not occur. if re- set, the pll clock, clock2 or clock2/16 is se- lected (depending on bit 0). bit 1= lock : pll locked-in this bit is read only. 0: the pll is turned off or not locked and cannot be selected as system clock source. 1: the pll is locked bit 0 = csu_cksel : csu clock select this bit is set and cleared by software. it also cleared by hardware when: C bits dx[2:0] (pllconf) are set to 111; C the quartz is stopped (by hardware or software); C wfi is executed while the lpowfi bit is set; C the xt_div16 bit (clk_flag) is forced to 0. this prevents the pll, when not yet locked, from providing an irregular clock. furthermore, a 0 stored in this bit speeds up the plls locking. 0: clock2 provides the system clock 1: the pll multiplier provides the system clock. note : setting the ckaf_sel bit overrides any other clock selection. resetting the xt_div16 bit overrides the csu_cksel selection (see figure 70 ex_ stp wdg res soft res xtstop xt_ div16 ckaf_ st loc k csu_ cksel 1
71/179 st92141 - reset and clock control unit (rccu) clock control registers (contd) pll configuration register (pllconf) r246 - read/write register page: 55 reset value: xx00 x111 bit 5:4 = mx[1:0] : pll multiplication factor . refer to table 15 pll multiplication factors for multiplier settings. bit 2:0 = dx[2:0] : pll output clock divider factor. refer to table 16 divider configuration for divider settings. table 15. pll multiplication factors table 16. divider configuration figure 31. rccu general timing 70 - - mx1 mx0 - dx2 dx1 dx0 mx1 mx0 clock2 x 10 14 00 10 11 8 01 6 dx2 dx1 dx0 ck 0 0 0 pll clock/1 0 0 1 pll clock/2 0 1 0 pll clock/3 0 1 1 pll clock/4 1 0 0 pll clock/5 1 0 1 pll clock/6 1 1 0 pll clock/7 111 clock2 (pll off, reset state) stop acknowledged stop external multiplier xtal intclk internal reset clock clock reset request (*) pll selected by user 20478xt xtal (**) pll lock-in time pll lock-in time 4 xt sys quartz start-up exit from reset 10239*clock2 switch to pll clock (*) wuimu pll turned on by user xtal/2 pll pll xtal/2 (**) +/- 1 t xtal 1
72/179 st92141 - reset and clock control unit (rccu) figure 32. rccu timing during stop (ck_af system clock) figure 33. low power wfi mode with a stopped quartz oscillator stop xtal clock request (*) 20478 x t xtal (**) 4 xt sys quartz start-up exit from stop 10239*clock2 acknowledged ck_af clock (*) from wuimu intclk reset ck_af selected ckaf_sel<-1 (**) +/- 1 t xtal intclk wfi state multiplier clock xtal clock interrupt xtals restart time pll lock-in time t sys =2 xt xtal pll l with: div2=1 ck_af clock (t sys =16* t ck_af ) xtstop<-0 csu_cksel<-1 ckaf_sel<-0 pll (t sys = t ck_af ) 1
73/179 st92141 - reset and clock control unit (rccu) 5.5 oscillator characteristics the on-chip oscillator circuit uses an inverting gate circuit with tri-state output. notes : owing to the q factor required, ceramic resonators may not provide a reliable oscillator source . oscout must not be directly used to drive exter- nal circuits. when the oscillator is stopped, oscout goes high impedance. the parallel resistor, r, is disconnected and the oscillator is disabled, forcing the internal clock, clock1, to a high level, and oscout to a high impedance state. to exit the halt condition and restart the oscilla- tor, an external reset pulse is required. it should be noted that, if the watchdog function is enabled, a halt instruction will not disable the os- cillator. this to avoid stopping the watchdog if a halt code is executed in error. when this occurs, the cpu will be reset when the watchdog times out or when an external reset is applied. figure 34. crystal oscillator table 17. crystal specification (5v) legend : c l1 , c l2 : maximum total capacitances on pins oscin and oscout (the value includes the external capaci- tance tied to the pin cl1 and cl2 plus the parasitic capac- itance of the board and of the device). note : the tables are relative to the fundamental quartz crystal only (not ceramic resonator). figure 35. internal oscillator schematic figure 36. external clock oscin oscout c l1 c l2 st9 crystal clock vr02116a 1m* *recommended for oscillator stability rs max (ohm) c l1 =c l2 = 56pf c l1 =c l2 = 47pf c l1 =c l2 = 22pf freq. = 3 mhz 270 350 850 freq. = 4 mhz 150 200 510 freq. = 5 mhz 110 120 340 vr02086a halt oscin oscout r in r out r oscin oscout clock input nc external clock vr02116b st9 1
74/179 st92141 - reset and clock control unit (rccu) 5.6 reset/stop manager the reset/stop manager resets the mcu when one of the three following events occurs: C a hardware reset, initiated by a low level on the reset pin. C a software reset, initiated by a halt instruction (when enabled). C a watchdog end of count condition. the low voltage detector (lvd) (see section 5.8) generates a reset when: C the power supply, when rising, is under the lvd v lvdr threshold. C the power supply, when falling, is under the lvd v lvdf threshold. the event which caused the last reset is flagged in the clk_flag register, by setting the sof- tres or the wdgres bits respectively; a hard- ware initiated reset will leave both these bits reset. the hardware reset overrides all other conditions and forces the st9 to the reset state. during re- set, the internal registers are set to their reset val- ues, where these are defined, and the i/o pins are set to the bidirectional weak pull-up mode. reset is asynchronous: as soon as the reset pin is driven low, a reset cycle is initiated. figure 37. oscillator start-up sequence and reset timing v dd max v dd min oscin intclk reset oscout pin 5.1 ms (*) vr02085a t start-up t intclk (*) with 4 mhz quartz 1
75/179 st92141 - reset and clock control unit (rccu) reset/stop manager (contd) the on-chip timer/watchdog generates a reset condition if the watchdog mode is enabled (wcr.wden cleared, r252 page 0), and if the programmed period elapses without the specific code (aah, 55h) written to the appropriate register. the input pin reset is not driven low by the on- chip reset generated by the timer/watchdog. when the reset pin goes high again, a delay occurs before exiting the reset state. subsequently a short boot routine is executed from the device internal boot rom, and control then passes to the user pro- gram. the boot routine sets the device characteristics and loads the correct values in the memory man- agement units pointer registers, so that these point to the physical memory areas as mapped in the specific device. the precise duration of this short boot routine varies from device to device, depending on the boot rom contents. at the end of the boot routine the program coun- ter will be set to the location specified in the reset vector located in the lowest two bytes of memory. 5.6.1 reset pin timing to improve the noise immunity of the device, the reset pin has a schmitt trigger input circuit with hysteresis. in addition, a filter will prevent an un- wanted reset in case of a single glitch of less than 50 ns on the reset pin. the device is certain to re- set if a negative pulse of more than 20s is ap- plied. when the reset pin goes high again, a delay of up to 4s will elapse before the rccu detects this rising front. from this event on, 20478 (about 5 ms with a 4mhz quartz) oscillator clock cycles (clock1) are counted before exiting the reset state (+-1 clock1 period depending on the delay between the positive edge the rccu detects and the first rising edge of clock1) if the st9 is a romless version, without on-chip program memory, the memory interface ports are set to external memory mode (i.e alternate func- tion) and the memory accesses are made to exter- nal program memory with wait cycles insertion. figure 38. recommended signal to be applied on reset pin v reset v cc 0.7 v cc 0.3 v cc 20 s minimum 1
76/179 st92141 - reset and clock control unit (rccu) 5.7 stop mode under control of the wake-up interrupt manage- ment unit (wuimu), the reset/stop manager can also stop all oscillators without resetting the de- vice. in stop mode all context information will be pre- served. during this condition the internal clock will be frozen in the high state. stop mode is entered by programming the wuimu registers (see wake-up / interrupt lines management unit (wuimu) on page 55.). an active transition on an external wake up line, exits the chip from stop mode and the mcu resumes execution after a delay of between 10239 clock2 periods and 10239 clock2 periods plus the oscillator start up time. on exiting from stop mode an interrupt is generat- ed and the ex_stp bit in clk_flag will be set, to indicate to the user program that the machine is exiting from stop mode. table 18. internal registers reset values register number system register reset value page 0 register reset value f (ssplr) undefined reserved e (ssphr) undefined (spicr) 00h d (usplr) undefined (spidr) undefined c (usphr) undefined (wcr) 7fh b (moder) e0h (wdtcr) 12h a (page ptr) undefined (wdtpr) undefined 9 (reg ptr 1) undefined (wdtlr) undefined 8 (reg ptr 0) undefined (wdthr) undefined 7 (flagr) undefined (nicr) 00h 6 (cicr) 87h (eivr) x2h 5 (port5) ffh (eiplr) ffh 4 (port4) ffh (eimr) 00h 3 (port3) ffh (eipr) 00h 2 (port2) ffh (eitr) 00h 1 (port1) ffh reserved 0 (port0) ffh reserved 1
77/179 st92141 - reset and clock control unit (rccu) figure 39. oscillator start-up sequence on exit from stop mode v dd max v dd min oscin stop oscout disactivation intclk t start-up 5.1 ms (*) < t intclk < 5.1 ms + t start-up (*) with 4mhz quartz and rccu programmed with xt_stop bit = 1 when read 1
78/179 st92141 - reset and clock control unit (rccu) 5.8 low voltage detector (lvd) to allow the integration of power management features in the application, the low voltage detec- tor function (lvd) generates a static reset when the v dd supply voltage is below a v lvdf reference value. this means that it secures the power-up as well as the power-down keeping the st9 in reset. the v lvdf reference value for a voltage drop is lower than the v lvdr reference value for power-on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: Cv lvdr when v dd is rising Cv lvdf when v dd is falling the lvd function is illustrated in figure 40 . provided the minimum v dd value (guaranteed for the oscillator frequency) is below v lvdf , the mcu can only be in two modes: C under full software control C in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. figure 40. low voltage detector vs reset v dd v lvdr reset v lvdf hysterisis v lvdhyst 1
79/179 st92141 - i/o ports 6 i/o ports 6.1 introduction st9 devices feature flexible individually program- mable multifunctional input/output lines. refer to the pin description chapter for specific pin alloca- tions. these lines, which are logically grouped as 8-bit ports, can be individually programmed to pro- vide digital input/output and analog input, or to connect input/output signals to the on-chip periph- erals as alternate pin functions. all ports can be in- dividually configured as an input, bi-directional, output or alternate function. in addition, pull-ups can be turned off for open-drain operation, and weak pull-ups can be turned on in their place, to avoid the need for off-chip resistive pull-ups. ports configured as open drain must never have voltage on the port pin exceeding v dd (refer to the electri- cal characteristics section). depending on the specific port, input buffers are software selectable to be ttl or cmos compatible, however on sch- mitt trigger ports, no selection is possible. 6.2 specific port configurations refer to the pin description chapter for a list of the specific port styles and reset values. 6.3 port control registers each port is associated with a data register (pxdr) and three control registers (pxc0, pxc1, pxc2). these define the port configuration and al- low dynamic configuration changes during pro- gram execution. port data and control registers are mapped into the register file as shown in fig- ure 41 . port data and control registers are treated just like any other general purpose register. there are no special instructions for port manipulation: any instruction that can address a register, can ad- dress the ports. data can be directly accessed in the port register, without passing through other memory or accumulator locations. figure 41. i/o register map group e group f page 2 group f page 3 group f page 43 system registers ffh reserved p7dr p9dr r255 feh p3c2 p7c2 p9c2 r254 fdh p3c1 p7c1 p9c1 r253 fch p3c0 p7c0 p9c0 r252 fbh reserved p6dr p8dr r251 fah p2c2 p6c2 p8c2 r250 f9h p2c1 p6c1 p8c1 r249 f8h p2c0 p6c0 p8c0 r248 f7h reserved reserved reserved r247 f6h p1c2 p5c2 r246 e5h p5dr r229 f5h p1c1 p5c1 r245 e4h p4dr r228 f4h p1c0 p5c0 r244 e3h p3dr r227 f3h reserved reserved r243 e2h p2dr r226 f2h p0c2 p4c2 r242 e1h p1dr r225 f1h p0c1 p4c1 r241 e0h p0dr r224 f0h p0c0 p4c0 r240 1
80/179 st92141 - i/o ports port control registers (contd) during reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output data register is set to ffh. this condition is also held after reset, except for ports 0 and 1 in rom- less devices, and can be redefined under software control. bidirectional ports without weak pull-ups are set in high impedance during reset. to ensure proper levels during reset, these ports must be externally connected to either v dd or v ss through external pull-up or pull-down resistors. other reset conditions may apply in specific st9 devices. 6.4 input/output bit configuration by programming the control bits pxc0.n and pxc1.n (see figure 42 ) it is possible to configure bit px.n as input, output, bidirectional or alternate function output, where x is the number of the i/o port, and n the bit within the port (n = 0 to 7). when programmed as input, it is possible to select the input level as ttl or cmos compatible by pro- gramming the relevant pxc2.n control bit. this option is not available on schmitt trigger ports. the output buffer can be programmed as push- pull or open-drain. a weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirec- tional (except where the weak pull-up option has been permanently disabled in the pin hardware as- signment). each pin of an i/o port may assume software pro- grammable alternate functions (refer to the de- vice pin description and to section 6.5 alter- nate function architecture). to output signals from the st9 peripherals, the port must be configured as af out. on st9 devices with a/d converter(s), configure the ports used for analog inputs as af in. the basic structure of the bit px.n of a general pur- pose port px is shown in figure 43 . independently of the chosen configuration, when the user addresses the port as the destination reg- ister of an instruction, the port is written to and the data is transferred from the internal data bus to the output master latches. when the port is ad- dressed as the source register of an instruction, the port is read and the data (stored in the input latch) is transferred to the internal data bus. when px.n is programmed as an input : (see figure 44 ). C the output buffer is forced tristate. C the data present on the i/o pin is sampled into the input latch at the beginning of each instruc- tion execution. C the data stored in the output master latch is copied into the output slave latch at the end of the execution of each instruction. thus, if bit px.n is reconfigured as an output or bidirectional, the data stored in the output slave latch will be re- flected on the i/o pin. 1
81/179 st92141 - i/o ports input/output bit configuration (contd) figure 42. control bits n table 19. port bit configuration table (n = 0, 1... 7; x = port number) (1) for a/d converter inputs. legend: x = port n = bit af = alternate function bid = bidirectional cmos= cmos standard input levels hi-z = high impedance in = input od = open drain out = output pp = push-pull ttl = ttl standard input levels wp = weak pull-up bit 7 bit n bit 0 pxc2 pxc27 pxc2n pxc20 pxc1 pxc17 pxc1n pxc10 pxc0 pxc07 pxc0n pxc00 general purpose i/o pins a/d pins pxc2n pxc1n pxc0n 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 pxn configuration bid bid out out in in af out af out af in pxn output type wp od od pp od hi-z hi-z pp od hi-z (1) pxn input type ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) cmos (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) ttl (or schmitt trigger) analog input 1
82/179 st92141 - i/o ports input/output bit configuration (contd) figure 43. basic structure of an i/o port pin figure 44. input configuration n n figure 45. output configuration n output slave latch output master latch input latch internal data bus i/o pin push-pull tristate open drain weak pull-up from peripheral output output input bidirectional alternate function to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts alternate function input output bidirectional output master latch input latch output slave latch internal data bus i/o pin tristate to peripheral inputs and ttl / cmos (or schmitt trigger) interrupts output master latch input latch output slave latch internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull to peripheral inputs and interrupts 1
83/179 st92141 - i/o ports input/output bit configuration (contd) when px.n is programmed as an output : ( figure 45 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data stored in the output master latch is copied both into the input latch and into the out- put slave latch, driving the i/o pin, at the end of the execution of the instruction. when px.n is programmed as bidirectional : ( figure 46 ) C the output buffer is turned on in an open-drain or weak pull-up configuration (except when dis- abled in hardware). C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the data stored in the output master latch is copied into the output slave latch, driving the i/ o pin, at the end of the execution of the instruc- tion. warning : due to the fact that in bidirectional mode the external pin is read instead of the output latch, particular care must be taken with arithme- tic/logic and boolean instructions performed on a bidirectional port pin. these instructions use a read-modify-write se- quence, and the result written in the port register depends on the logical level present on the exter- nal pin. this may bring unwanted modifications to the port output register content. for example: port register content, 0fh external port value, 03h (bits 3 and 2 are externally forced to 0) a bset instruction on bit 7 will return: port register content, 83h external port value, 83h (bits 3 and 2 have been cleared). to avoid this situation, it is suggested that all oper- ations on a port, using at least one bit in bidirec- tional mode, are performed on a copy of the port register, then transferring the result with a load in- struction to the i/o port. when px.n is programmed as a digital alter- nate function output : ( figure 47 ) C the output buffer is turned on in an open-drain or push-pull configuration. C the data present on the i/o pin is sampled into the input latch at the beginning of the execution of the instruction. C the signal from an on-chip function is allowed to load the output slave latch driving the i/o pin. signal timing is under control of the alternate function. if no alternate function is connected to px.n, the i/o pin is driven to a high level when in push-pull configuration, and to a high imped- ance state when in open drain configuration. figure 46. bidirectional configuration n n figure 47. alternate function configuration n n n n n n output master latch input latch output slave latch internal data bus i/o pin weak pull-up ttl (or schmitt trigger) open drain to peripheral inputs and interrupts input latch from internal data bus i/o pin open drain ttl (or schmitt trigger) push-pull peripheral output to peripheral inputs and interrupts output slave latch 1
84/179 st92141 - i/o ports 6.5 alternate function architecture each i/o pin may be connected to three different types of internal signal: C data bus input/output C alternate function input C alternate function output 6.5.1 pin declared as i/o a pin declared as i/o, is connected to the i/o buff- er. this pin may be an input, an output, or a bidi- rectional i/o, depending on the value stored in (pxc2, pxc1 and pxc0). 6.5.2 pin declared as an alternate function input a single pin may be directly connected to several alternate function inputs. in this case, the user must select the required input mode (with the pxc2, pxc1, pxc0 bits) and enable the selected alternate function in the control register of the peripheral. no specific port configuration is re- quired to enable an alternate function input, since the input buffer is directly connected to each alter- nate function module on the shared pin. as more than one module can use the same input, it is up to the user software to enable the required module as necessary. parallel i/os remain operational even when using an alternate function input. the exception to this is when an i/o port bit is perma- nently assigned by hardware as an a/d bit. in this case , after software programming of the bit in af- od-ttl, the alternate function output is forced to logic level 1. the analog voltage level on the cor- responding pin is directly input to the a/d (see fig- ure 48 ). figure 48. a/d input configuration 6.5.3 pin declared as an alternate function output the user must select the af out configuration using the pxc2, pxc1, pxc0 bits. several alter- nate function outputs may drive a common pin. in such case, the alternate function output signals are logically anded before driving the common pin. the user must therefore enable the required alternate function output by software. warning : when a pin is connected both to an al- ternate function output and to an alternate function input, it should be noted that the output signal will always be present on the alternate function input. 6.6 i/o status after wfi, halt and reset the status of the i/o ports during the wait for in- terrupt, halt and reset operational modes is shown in the following table. the external memory interface ports are shown separately. if only the in- ternal memory is being used and the ports are act- ing as i/o, the status is the same as shown for the other i/o ports. input latch internal data bus i/o pin tristate input buffer output slave latch output master latch towards a/d converter gnd mode ext. mem - i/o ports i/o ports p0 p1, p2, p6, p9 wfi high imped- ance or next address (de- pending on the last memory op- eration per- formed on port) next address not affected (clock outputs running) halt high imped- ance next address not affected (clock outputs stopped) reset alternate function push- pull (romless device) bidirectional weak pull-up (high im- pedance when disa- bled in hardware). 1
85/179 st92141 - timer/watchdog (wdt) 7 on-chip peripherals 7.1 timer/watchdog (wdt) important note: this chapter is a generic descrip- tion of the wdt peripheral. however depending on the st9 device, some or all of wdt interface signals described may not be connected to exter- nal pins. for the list of wdt pins present on the st9 device, refer to the device pinout description in the first section of the data sheet. 7.1.1 introduction the timer/watchdog (wdt) peripheral consists of a programmable 16-bit timer and an 8-bit prescal- er. it can be used, for example, to: C generate periodic interrupts C measure input signal pulse widths C request an interrupt after a set number of events C generate an output signal waveform C act as a watchdog timer to monitor system in- tegrity the main wdt registers are: C control register for the input, output and interrupt logic blocks (wdtcr) C 16-bit counter register pair (wdthr, wdtlr) C prescaler register (wdtpr) the hardware interface consists of up to five sig- nals: C wdin external clock input C wdout square wave or pwm signal output C int0 external interrupt input C nmi non-maskable interrupt input C hw0sw1 hardware/software watchdog ena- ble. figure 49. timer/watchdog block diagram int0 1 input & clock control logic inen inmd1 inmd2 wdtpr 8-bit prescaler wdtrh, wdtrl 16-bit intclk/4 wdt outmd wrout output control logic interrupt control logic end of count reset top level interrupt request outen mux wdout 1 iaos tlis inta0 request nmi 1 wdgen hw0sw1 1 wdin 1 mux downcounter clock 1 pin not present on some st9 devices . 9
86/179 st92141 - timer/watchdog (wdt) timer/watchdog (contd) 7.1.2 functional description 7.1.2.1 external signals the hw0sw1 pin can be used to permanently en- able watchdog mode. refer to section 7.1.3.1 on page 87. the wdin input pin can be used in one of four modes: C event counter mode C gated external input mode C triggerable input mode C retriggerable input mode the wdout output pin can be used to generate a square wave or a pulse width modulated signal. an interrupt, generated when the wdt is running as the 16-bit timer/counter, can be used as a top level interrupt or as an interrupt source connected to channel a0 of the external interrupt structure (replacing the int0 interrupt input). the counter can be driven either by an external clock, or internally by intclk divided by 4. 7.1.2.2 initialisation the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be loaded with initial val- ues before starting the timer/counter. if this is not done, counting will start with reset values. 7.1.2.3 start/stop the st_sp bit enables downcounting. when this bit is set, the timer will start at the beginning of the following instruction. resetting this bit stops the counter. if the counter is stopped and restarted, counting will resume from the last value unless a new con- stant has been entered in the timer registers (wdtrl, wdtrh). a new constant can be written in the wdtrh, wdtrl, wdtpr registers while the counter is running. the new value of the wdtrh, wdtrl registers will be loaded at the next end of count (eoc) condition while the new value of the wdtpr register will be effective immediately. end of count is when the counter is 0. when watchdog mode is enabled the state of the st_sp bit is irrelevant. 7.1.2.4 single/continuous mode the s_c bit allows selection of single or continu- ous mode.this mode bit can be written with the timer stopped or running. it is possible to toggle the s_c bit and start the counter with the same in- struction. single mode on reaching the end of count condition, the timer stops, reloads the constant, and resets the start/ stop bit. software can check the current status by reading this bit. to restart the timer, set the start/ stop bit. note: if the timer constant has been modified dur- ing the stop period, it is reloaded at start time. continuous mode on reaching the end of count condition, the coun- ter automatically reloads the constant and restarts. it is stopped only if the start/stop bit is reset. 7.1.2.5 input section if the timer/counter input is enabled (inen bit) it can count pulses input on the wdin pin. other- wise it counts the internal clock/4. for instance, when intclk = 24mhz, the end of count rate is: 2.79 seconds for maximum count (timer const. = ffffh, prescaler const. = ffh) 166 ns for minimum count (timer const. = 0000h, prescaler const. = 00h) the input pin can be used in one of four modes: C event counter mode C gated external input mode C triggerable input mode C retriggerable input mode the mode is configurable in the wdtcr. 7.1.2.6 event counter mode in this mode the timer is driven by the external clock applied to the input pin, thus operating as an event counter. the event is defined as a high to low transition of the input signal. spacing between trailing edges should be at least 8 intclk periods (or 333ns with intclk = 24mhz). counting starts at the next input event after the st_sp bit is set and stops when the st_sp bit is reset. 9
87/179 st92141 - timer/watchdog (wdt) timer/watchdog (contd) 7.1.2.7 gated input mode this mode can be used for pulse width measure- ment. the timer is clocked by intclk/4, and is started and stopped by means of the input pin and the st_sp bit. when the input pin is high, the tim- er counts. when it is low, counting stops. the maximum input pin frequency is equivalent to intclk/8. 7.1.2.8 triggerable input mode the timer (clocked internally by intclk/4) is started by the following sequence: C setting the start-stop bit, followed by C a high to low transition on the input pin. to stop the timer, reset the st_sp bit. 7.1.2.9 retriggerable input mode in this mode, the timer (clocked internally by intclk/4) is started by setting the st_sp bit. a high to low transition on the input pin causes counting to restart from the initial value. when the timer is stopped (st_sp bit reset), a high to low transition of the input pin has no effect. 7.1.2.10 timer/counter output modes output modes are selected by means of the out- en (output enable) and outmd (output mode) bits of the wdtcr register. no output mode (outen = 0) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outen = 1, outmd = 0) the timer outputs a signal with a frequency equal to half the end of count repetition rate on the wd- out pin. with an intclk frequency of 20mhz, this allows a square wave signal to be generated whose period can range from 400ns to 6.7 sec- onds. pulse width modulated output mode (outen = 1, outmd = 1) the state of the wrout bit is transferred to the output pin (wdout) at the end of count, and is held until the next end of count condition. the user can thus generate pwm signals by modifying the status of the wrout pin between end of count events, based on software counters decre- mented by the timer watchdog interrupt. 7.1.3 watchdog timer operation this mode is used to detect the occurrence of a software fault, usually generated by external inter- ference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. the watchdog, when enabled, resets the mcu, unless the pro- gram executes the correct write sequence before expiry of the programmed time period. the appli- cation program must be designed so as to correct- ly write to the wdtlr watchdog register at regu- lar intervals during all phases of normal operation. 7.1.3.1 hardware watchdog/software watchdog the hw0sw1 pin (when available) selects hard- ware watchdog or software watchdog. if hw0sw1 is held low: C the watchdog is enabled by hardware immedi- ately after an external reset. (note: software re- set or watchdog reset have no effect on the watchdog enable status). C the initial counter value (ffffh) cannot be mod- ified, however software can change the prescaler value on the fly. C the wdgen bit has no effect. (note: it is not forced low). if hw0sw1 is held high, or is not present: C the watchdog can be enabled by resetting the wdgen bit. 7.1.3.2 starting the watchdog in watchdog mode the timer is clocked by intclk/4. if the watchdog is software enabled, the time base must be written in the timer registers before enter- ing watchdog mode by resetting the wdgen bit. once reset, this bit cannot be changed by soft- ware. if the watchdog is hardware enabled, the time base is fixed by the reset value of the registers. resetting wdgen causes the counter to start, re- gardless of the value of the start-stop bit. in watchdog mode, only the prescaler constant may be modified. if the end of count condition is reached a system reset is generated. 9
88/179 st92141 - timer/watchdog (wdt) timer/watchdog (contd) 7.1.3.3 preventing watchdog system reset in order to prevent a system reset, the sequence aah, 55h must be written to wdtlr (watchdog timer low register). once 55h has been written, the timer reloads the constant and counting re- starts from the preset value. to reload the counter, the two writing operations must be performed sequentially without inserting other instructions that modify the value of the wdtlr register between the writing operations. the maximum allowed time between two reloads of the counter depends on the watchdog timeout period. 7.1.3.4 non-stop operation in watchdog mode, a halt instruction is regarded as illegal. execution of the halt instruction stops further execution by the cpu and interrupt ac- knowledgment, but does not stop intclk, cpu- clk or the watchdog timer, which will cause a system reset when the end of count condition is reached. furthermore, st_sp, s_c and the input mode selection bits are ignored. hence, regard- less of their status, the counter always runs in continuous mode, driven by the internal clock. the output mode should not be enabled, since in this context it is meaningless. figure 50. watchdog timer mode timer start counting wri te wdtrh,wdtrl wd en=0 write aah,55h into wdtrl reset software fail (e.g. infinite loop) or peripheral fail va00220 produce count reload value count g 9
89/179 st92141 - timer/watchdog (wdt) timer/watchdog (contd) 7.1.4 wdt interrupts the timer/watchdog issues an interrupt request at every end of count, when this feature is ena- bled. a pair of control bits, ia0s (eivr.1, interrupt a0 se- lection bit) and tlis (eivr.2, top level input se- lection bit) allow the selection of 2 interrupt sources (timer/watchdog end of count, or external pin) handled in two different ways, as a top level non maskable interrupt (software reset), or as a source for channel a0 of the external interrupt logic. a block diagram of the interrupt logic is given in figure 51 . note: software traps can be generated by setting the appropriate interrupt pending bit. table 20 interrupt configuration below, shows all the possible configurations of interrupt/reset sources which relate to the timer/watchdog. a reset caused by the watchdog will set bit 6, wdgres of r242 - page 55 (clock flag regis- ter). see section clock control regis- ters . figure 51. interrupt sources table 20. interrupt configuration legend: wdg = watchdog function sw trap = software trap note: if ia0s and tlis = 0 (enabling the watchdog eoc as interrupt source for both top level and inta0 interrupts), only the inta0 interrupt is taken into account. timer watchdog reset wdgen (wcr.6) inta0 request ia0s (eivr.1) mux 0 1 int0 mux 0 1 top level interrupt request va00293 tlis (eivr.2) nmi control bits enabled sources operating mode wdgen ia0s tlis reset inta0 top level 0 0 0 0 0 0 1 1 0 1 0 1 wdg/ext reset wdg/ext reset wdg/ext reset wdg/ext reset sw trap sw trap ext pin ext pin sw trap ext pin sw trap ext pin watchdog watchdog watchdog watchdog 1 1 1 1 0 0 1 1 0 1 0 1 ext reset ext reset ext reset ext reset timer timer ext pin ext pin timer ext pin timer ext pin timer timer timer timer 9
90/179 st92141 - timer/watchdog (wdt) timer/watchdog (contd) 7.1.5 register description the timer/watchdog is associated with 4 registers mapped into group f, page 0 of the register file. wdthr : timer/watchdog high register wdtlr : timer/watchdog low register wdtpr : timer/watchdog prescaler register wdtcr : timer/watchdog control register three additional control bits are mapped in the fol- lowing registers on page 0: watchdog mode enable, (wcr.6) top level interrupt selection, (eivr.2) interrupt a0 channel selection, (eivr.1) note : the registers containing these bits also con- tain other functions. only the bits relevant to the operation of the timer/watchdog are shown here. counter register this 16-bit register (wdtlr, wdthr) is used to load the 16-bit counter value. the registers can be read or written on the fly. timer/watchdog high register (wdthr) r248 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = r[15:8] counter most significant bits . timer/watchdog low register (wdtlr) r249 - read/write register page: 0 reset value: 1111 1111b (ffh) bits 7:0 = r[7:0] counter least significant bits. timer/watchdog prescaler register (wdtpr) r250 - read/write register page: 0 reset value: 1111 1111 (ffh) bits 7:0 = pr[7:0] prescaler value. a programmable value from 1 (00h) to 256 (ffh). warning : in order to prevent incorrect operation of the timer/watchdog, the prescaler (wdtpr) and counter (wdtrl, wdtrh) registers must be ini- tialised before starting the timer/watchdog. if this is not done, counting will start with the reset (un-in- itialised) values. watchdog timer control register (wdtcr) r251- read/write register page: 0 reset value: 0001 0010 (12h) bit 7 = st_sp : start/stop bit . this bit is set and cleared by software. 0: stop counting 1: start counting (see warning above) bit 6 = s_c : single/continuous . this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:4 = inmd[1:2] : input mode selection bits . these bits select the input mode: 70 r15 r14 r13 r12 r11 r10 r9 r8 70 r7 r6 r5 r4 r3 r2 r1 r0 70 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 70 st_sp s_c inmd1 inmd2 inen outmd wrout outen inmd1 inmd2 input mode 0 0 event counter 0 1 gated input (reset value) 1 0 triggerable input 1 1 retriggerable input 9
91/179 st92141 - timer/watchdog (wdt) timer/watchdog (contd) bit 3 = inen : input enable . this bit is set and cleared by software. 0: disable input section 1: enable input section bit 2 = outmd : output mode. this bit is set and cleared by software. 0: the output is toggled at every end of count 1: the value of the wrout bit is transferred to the output pin on every end of count if outen=1. bit 1 = wrout : write out . the status of this bit is transferred to the output pin when outmd is set; it is user definable to al- low pwm output (on reset wrout is set). bit 0 = outen : output enable bit . this bit is set and cleared by software. 0: disable output 1: enable output wait control register (wcr) r252 - read/write register page: 0 reset value: 0111 1111 (7fh) bit 6 = wdgen : watchdog enable (active low). resetting this bit via software enters the watch- dog mode. once reset, it cannot be set anymore by the user program. at system reset, the watch- dog mode is disabled. note: this bit is ignored if the hardware watchdog option is enabled by pin hw0sw1 (if available). external interrupt vector register (eivr) r246 - read/write register page: 0 reset value: xxxx 0110 (x6h) bit 2 = tlis : top level input selection . this bit is set and cleared by software. 0: watchdog end of count is tl interrupt source 1: nmi is tl interrupt source bit 1 = ia0s : interrupt channel a0 selection. this bit is set and cleared by software. 0: watchdog end of count is inta0 source 1: external interrupt pin is inta0 source warning : to avoid spurious interrupt requests, the ia0s bit should be accessed only when the in- terrupt logic is disabled (i.e. after the di instruc- tion). it is also necessary to clear any possible in- terrupt pending requests on channel a0 before en- abling this interrupt channel. a delay instruction (e.g. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ia0s write instruction. other bits are described in the interrupt section. 70 xwdgenxxxxxx 70 x x x x x tlis ia0s x 9
92/179 st92141 - standard timer (stim) 7.2 standard timer (stim) important note: this chapter is a generic descrip- tion of the stim peripheral. depending on the st9 device, some or all of the interface signals de- scribed may not be connected to external pins. for the list of stim pins present on the particular st9 device, refer to the pinout description in the first section of the data sheet. 7.2.1 introduction the standard timer includes a programmable 16- bit down counter and an associated 8-bit prescaler with single and continuous counting modes capa- bility. the standard timer uses an input pin (stin) and an output (stout) pin. these pins, when available, may be independent pins or connected as alternate functions of an i/o port bit. stin can be used in one of four programmable in- put modes: C event counter, C gated external input mode, C triggerable input mode, C retriggerable input mode. stout can be used to generate a square wave or pulse width modulated signal. the standard timer is composed of a 16-bit down counter with an 8-bit prescaler. the input clock to the prescaler can be driven either by an internal clock equal to intclk divided by 4, or by clock2 derived directly from the external oscilla- tor, divided by device dependent prescaler value, thus providing a stable time reference independ- ent from the pll programming or by an external clock connected to the stin pin. the standard timer end of count condition is able to generate an interrupt which is connected to one of the external interrupt channels. the end of count condition is defined as the counter underflow, whenever 00h is reached. figure 52. standard timer block diagram n stout 1 external input & clock control logic inen inmd1 inmd2 stp 8-bit prescaler sth,stl 16-bit standard timer clock outmd1 outmd2 output control logic interrupt control logic end of count ints interrupt request clock2/x stin 1 interrupt 1 downcounter (see note 2) note 2: depending on device, the source of the input & clock control logic block may be permanently connected either to stin or the rccu signal clock2/x. in devices without stin and clock2, the intclk/4 mux note 1: pin not present on all st9 devices . inen bit must be held at 0. 9
93/179 st92141 - standard timer (stim) standard timer (contd) 7.2.2 functional description 7.2.2.1 timer/counter control start-stop count. the st-sp bit (stc.7) is used in order to start and stop counting. an instruction which sets this bit will cause the standard timer to start counting at the beginning of the next instruc- tion. resetting this bit will stop the counter. if the counter is stopped and restarted, counting will resume from the value held at the stop condi- tion, unless a new constant has been entered in the standard timer registers during the stop peri- od. in this case, the new constant will be loaded as soon as counting is restarted. a new constant can be written in sth, stl, stp registers while the counter is running. the new value of the sth and stl registers will be loaded at the next end of count condition, while the new value of the stp register will be loaded immedi- ately. warning: in order to prevent incorrect counting of the standard timer, the prescaler (stp) and counter (stl, sth) registers must be initialised before the starting of the timer. if this is not done, counting will start with the reset values (sth=ffh, stl=ffh, stp=ffh). single/continuous mode. the s-c bit (stc.6) selects between the single or continuous mode. single mode: at the end of count, the standard timer stops, reloads the constant and resets the start/stop bit (the user programmer can inspect the timer current status by reading this bit). setting the start/stop bit will restart the counter. continuous mode: at the end of the count, the counter automatically reloads the constant and re- starts. it is only stopped by resetting the start/stop bit. the s-c bit can be written either with the timer stopped or running. it is possible to toggle the s-c bit and start the standard timer with the same in- struction. 7.2.2.2 standard timer input modes (st9 devices with standard timer input stin) bits inmd2, inmd1 and inen are used to select the input modes. the input enable (inen) bit ena- bles the input mode selected by the inmd2 and inmd1 bits. if the input is disabled (inen="0"), the values of inmd2 and inmd1 are not taken into ac- count. in this case, this unit acts as a 16-bit timer (plus prescaler) directly driven by intclk/4 and transitions on the input pin have no effect. event counter mode (inmd1 = "0", inmd2 = "0") the standard timer is driven by the signal applied to the input pin (stin) which acts as an external clock. the unit works therefore as an event coun- ter. the event is a high to low transition on stin. spacing between trailing edges should be at least the period of intclk multiplied by 8 (i.e. the max- imum standard timer input frequency is 3 mhz with intclk = 24mhz). gated input mode (inmd1 = "0", inmd2 = 1) the timer uses the internal clock (intclk divided by 4) and starts and stops the timer according to the state of stin pin. when the status of the stin is high the standard timer count operation pro- ceeds, and when low, counting is stopped. triggerable input mode (inmd1 = 1, inmd2 = 0) the standard timer is started by: a) setting the start-stop bit, and b) a high to low (low trigger) transition on stin. in order to stop the standard timer in this mode, it is only necessary to reset the start-stop bit. retriggerable input mode (inmd1 = 1, inmd2 = 1) in this mode, when the standard timer is running (with internal clock), a high to low transition on stin causes the counting to start from the last constant loaded into the stl/sth and stp regis- ters. when the standard timer is stopped (st-sp bit equal to zero), a high to low transition on stin has no effect. 7.2.2.3 time base generator (st9 devices without standard timer input stin) for devices where stin is replaced by a connec- tion to clock2, the condition (inmd1 = 0, inmd2 = 0) will allow the standard timer to gen- erate a stable time base independent from the pll programming. 9
94/179 st92141 - standard timer (stim) standard timer (contd) 7.2.2.4 standard timer output modes output modes are selected using 2 bits of the stc register: outmd1 and outmd2. no output mode (outmd1 = 0, outmd2 = 0) the output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the i/o pin. square wave output mode (outmd1 = 0, outmd2 = 1) the standard timer toggles the state of the stout pin on every end of count condition. with intclk = 24mhz, this allows generation of a square wave with a period ranging from 333ns to 5.59 seconds. pwm output mode (outmd1 = 1) the value of the outmd2 bit is transferred to the stout output pin at the end of count. this al- lows the user to generate pwm signals, by modi- fying the status of outmd2 between end of count events, based on software counters decremented on the standard timer interrupt. 7.2.3 interrupt selection the standard timer may generate an interrupt re- quest at every end of count. bit 2 of the stc register (ints) selects the inter- rupt source between the standard timer interrupt and the external interrupt pin. thus the standard timer interrupt uses the interrupt channel and takes the priority and vector of the external inter- rupt channel. if ints is set to 1, the standard timer interrupt is disabled; otherwise, an interrupt request is gener- ated at every end of count. note: when enabling or disabling the standard timer interrupt (writing ints in the stc register) an edge may be generated on the interrupt chan- nel, causing an unwanted interrupt. to avoid this spurious interrupt request, the ints bit should be accessed only when the interrupt log- ic is disabled (i.e. after the di instruction). it is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. a delay instruction (i.e. a nop instruction) must be inserted between the reset of the interrupt pending bit and the ints write instruction. 7.2.4 register mapping depending on the st9 device there may be up to 4 standard timers (refer to the block diagram in the first section of the data sheet). each standard timer has 4 registers mapped into page 11 in group f of the register file in the register description on the following page, register addresses refer to stim0 only. note: the four standard timers are not implement- ed on all st9 devices. refer to the block diagram of the device for the number of timers. std timer register register address stim0 sth0 r240 (f0h) stl0 r241 (f1h) stp0 r242 (f2h) stc0 r243 (f3h) stim1 sth1 r244 (f4h) stl1 r245 (f5h) stp1 r246 (f6h) stc1 r247 (f7h) stim2 sth2 r248 (f8h) stl2 r249 (f9h) stp2 r250 (fah) stc2 r251 (fbh) stim3 sth3 r252 (fch) stl3 r253 (fdh) stp3 r254 (feh) stc3 r255 (ffh) 9
95/179 st92141 - standard timer (stim) standard timer (contd) 7.2.5 register description counter high byte register (sth) r240 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[15:8] : counter high-byte. counter low byte register (stl) r241 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = st.[7:0] : counter low byte. writing to the sth and stl registers allows the user to enter the standard timer constant, while reading it provides the counters current value. thus it is possible to read the counter on-the-fly. standard timer prescaler register (stp) r242 - read/write register page: 11 reset value: 1111 1111 (ffh) bits 7:0 = stp.[7:0] : prescaler. the prescaler value for the standard timer is pro- grammed into this register. when reading the stp register, the returned value corresponds to the programmed data instead of the current data. 00h: no prescaler 01h: divide by 2 ffh: divide by 256 standard timer control register (stc) r243 - read/write register page: 11 reset value: 0001 0100 (14h) bit 7 = st-sp : start-stop bit. this bit is set and cleared by software. 0: stop counting 1: start counting bit 6 = s-c : single-continuous mode select. this bit is set and cleared by software. 0: continuous mode 1: single mode bits 5:4 = inmd[1:2] : input mode selection. these bits select the input functions as shown in section 7.2.2.2, when enabled by inen. bit 3 = inen : input enable. this bit is set and cleared by software. if neither the stin pin nor the clock2 line are present, inen must be 0. 0: input section disabled 1: input section enabled bit 2 = ints : interrupt selection. 0: standard timer interrupt enabled 1: standard timer interrupt is disabled and the ex- ternal interrupt pin is enabled. bits 1:0 = outmd[1:2] : output mode selection. these bits select the output functions as described in section 7.2.2.4. 70 st.15 st.14 st.13 st.12 st.11 st.10 st.9 st.8 70 st.7 st.6 st.5 st.4 st.3 st.2 st.1 st.0 70 stp.7 stp.6 stp.5 stp.4 stp.3 stp.2 stp.1 stp.0 70 st-sp s-c inmd1 inmd2 inen ints outmd1 outmd2 inmd1 inmd2 mode 00 event counter mode 01 gated input mode 10 triggerable mode 11 retriggerable mode outmd1 outmd2 mode 00 no output mode 01 square wave output mode 1x pwm output mode 9
96/179 st92141 - extended function timer (eft) 7.3 extended function timer (eft) 7.3.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the intclk prescaler. 7.3.2 main features n programmable prescaler: intclk divided by 2, 4 or 8. n overflow status flag and maskable interrupts n external clock input (must be at least 4 times slower than the intclk clock speed) with the choice of active edge n output compare functions with C 2 dedicated 16-bit registers C 2 dedicated programmable signals C 2 dedicated status flags C 1 dedicated maskable interrupt n input capture functions with C 2 dedicated 16-bit registers C 2 dedicated active edge selection signals C 2 dedicated status flags C 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports* n up to 3 separate timer interrupts or a global interrupt (depending on device) mapped on external interrupt channels: C ici: timer input capture interrupt. C oci: timer output compare interrupt. C toi: timer overflow interrupt. C efti: timer global interrupt (replaces ici, oci and toi). the block diagram is shown in figure 53 . table 21. eft pin naming conventions *note 1: some external pins are not available on all devices. refer to the device pin out description. *note 2: refer to the device interrupt description, to see if a single timer interrupt is used, or three separate interrupts. 7.3.3 functional description 7.3.3.1 counter the principal block of the programmable timer is a 16-bit free running counter and its associated 16-bit registers: counter registers C counter high register (chr) is the most sig- nificant byte (msb). C counter low register (clr) is the least sig- nificant byte (lsb). alternate counter registers C alternate counter high register (achr) is the most significant byte (msb). C alternate counter low register (aclr) is the least significant byte (lsb). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (overflow flag), (see note page 98 ). writing in the clr register or aclr register resets the free running counter to the fffch value. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 22 clock control bits . the value in the counter register re- peats every 131.072, 262.144 or 524.288 intclk cycles depending on the cc1 and cc0 bits. function eft0 eft1 eftn input capture 1 - icap1 icapa0 icapa1 icapan input capture 2 - icap2 icapb0 icapb1 icapbn output compare 1 - ocmp1 ocmpa0 ocmpa1 ocmpan output compare 2 - ocmp2 ocmpb0 ocmpb1 ocmpbn 9
97/179 st92141 - extended function timer (eft) extended function timer (contd) figure 53. timer block diagram 1 mcu-peripheral interface counter alternate register output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st9 internal bus latch1 ocmp1 icap1 extclk intclk efti icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 cr1 cr2 sr 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc1 cc0 16 bit free running counter 0 0 eftis icis ocis tois 0 0 cr3 0 10 10 10 eici eoc etoi eefti to i o ci i ci 9
98/179 st92141 - extended function timer (eft) extended function timer (contd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the msb first, then the lsb value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the lsb of the count value at the time of the read. an overflow occurs when the counter rolls over from ffffh to 0000h then: C the tof bit of the sr register is set. C a timer interrupt is generated if: C toie bit of the cr1 register is set C tois bit of the cr3 register is set (or eftis bit if only global interrupt is available). if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done by: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. this feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the reset count (mcu awakened by a reset). 7.3.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in cr2 register. the status of the exedg bit determines the type of level transition on the external clock pin ext- clk that will trigger the free running counter. the counter is synchronised with the falling edge of intclk. at least four falling edges of the intclk must oc- cur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the intclk fre- quency. lsb is buffered read msb at t0 read lsb returns the buffered lsb value at t0 at t0 + d t other instructions beginning of the sequence sequence completed 9
99/179 st92141 - extended function timer (eft) extended function timer (contd) figure 54. counter timing diagram, intclk divided by 2 figure 55. counter timing diagram, intclk divided by 4 figure 56. counter timing diagram, intclk divided by 8 intclk fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register overflow flag tof fffc fffd 0000 0001 intclk internal reset timer clock counter register overflow flag tof intclk internal reset timer clock counter register overflow flag tof fffc fffd 0000 9
100/179 st92141 - extended function timer (eft) extended function timer (contd) 7.3.3.3 input capture in this section, the index, i , may be 1 or 2. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition detected by the icap i pin (see figure 5). ic i rregister is a read-only register. the active transition is software programmable through the iedg i bit of the control register (cr i ). timing resolution is one count of the free running counter: ( intclk /cc[1:0] ). procedure to use the input capture function select the follow- ing in the cr2 register: C select the timer clock (cc[1:0] (see table 22 clock control bits ). C select the edge of the active transition on the icap2 pin with the iedg2 bit. and select the following in the cr1 register: C set the icie bit to generate an interrupt after an input capture. C select the edge of the active transition on the icap1 pin with the iedg1 bit. when an input capture occurs: C icf i bit is set. C the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 58 ). C a timer interrupt is generated if the icie bit is set and the icis bit (or eftis bit if only global inter- rupt is available) is set. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request is done by: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. note: after reading the ic i hr register, transfer of input capture data is inhibited until the ic i lr regis- ter is also read. the ic i r register always contains the free running counter value which corresponds to the most re- cent input capture. ms byte ls byte ic i ric i hr ic i lr 9
101/179 st92141 - extended function timer (eft) extended function timer (contd) figure 57. input capture block diagram figure 58. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r ic2r edge detect circuit1 ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge. 9
102/179 st92141 - extended function timer (eft) extended function timer (contd) 7.3.3.4 output compare in this section, the index, i , may be 1 or 2. this function can be used to control an output waveform or indicating when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: C assigns pins with a programmable value if the oc i e bit is set C sets a flag in the status register C generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the free run- ning counter each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( intclk / cc[1:0] ). procedure to use the output compare function, select the fol- lowing in the cr2 register: C set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i function. C select the timer clock cc[1:0] (see table 22 clock control bits ). and select the following in the cr1 register: C select the olvl i bit to applied to the ocmp i pins after the match occurs. C set the ocie and ocis bits (or eftis bit if only global interrupt is available) to generate an inter- rupt if it is needed. when match is found: C ocf i bit is set. C the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset and stays low until valid compares change it to olvl i level). C a timer interrupt is generated if the ocie bit is set in the cr2 register and ocis bit (or eftis bit if only global interrupt is available) is set in the cr3 register. clearing the output compare interrupt request is done by: 3. reading the sr register while the ocf i bit is set. 4. an access (read or write) to the oc i lr register. note: after a processor write cycle to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. if the oc i e bit is not set, the ocmp i pin is a gen- eral i/o port and the olvl i bit will not appear when match is found but an interrupt could be gen- erated if the ocie bit is set. the value in the 16-bit oc i r register and the olvl i bit should be changed after each success- ful comparison in order to control an output wave- form or establish a new elapsed timeout. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = desired output compare period (in seconds) intclk = internal clock frequency cc1-cc0 = timer clock prescaler the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: C write to the oc i hr register (further compares are inhibited). C read the sr register (first step of the clearance of the ocf i bit, which may be already set). C write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r = d t * intclk (cc1.cc0) 9
103/179 st92141 - extended function timer (eft) extended function timer (contd) figure 59. output compare block diagram figure 60. output compare timing diagram, internal clock divided by 2 output compare 16-bit circuit oc1r 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r intclk timer clock counter output compare register compare register latch ocfi and ocmpi pin (olvli=1) cpu writes ffff ffff fffd fffd fffe ffff 0000 fffc 9
104/179 st92141 - extended function timer (eft) extended function timer (contd) 7.3.3.5 forced compare mode in this section i may represent 1 or 2. the following bits of the cr1 register are used: when the folv i bit is set, the olvl i bit is copied to the ocmp i pin. the olvl i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is not set, and thus no interrupt re- quest is generated. 7.3.3.6 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode, select the following in the the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. C select the edge of the active transition on the icap1 pin with the iedg1 bit . and select the following in the cr2 register: C set the oc1e bit, the ocmp1 pin is then dedi- cated to the output compare 1 function. C set the opm bit. C select the timer clock cc[1:0] (see table 22 clock control bits ). load the oc1r register with the value corre- sponding to the length of the pulse (see the formu- la in section 7.3.3.7). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin. when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 61 ). note: the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. the icf1 bit is set when an active edge occurs and can generate an interrupt if the icie bit is set. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. figure 61. one pulse mode timing folv2 folv1 olvl2 olvl1 event occurs counter is initialized to fffch ocmp1 = olvl2 counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle counter .... fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 9
105/179 st92141 - extended function timer (eft) extended function timer (contd) 7.3.3.7 pulse width modulation mode pulse width modulation mode enables the gener- ation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register. procedure to use pulse width modulation mode select the fol- lowing in the cr1 register: C using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful com- parison with oc1r register. C using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful com- parison with oc2r register. and select the following in the cr2 register: C set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. C set the pwm bit. C select the timer clock cc[1:0] bits (see table 22 clock control bits ). load the oc2r register with the value corre- sponding to the period of the signal. load the oc1r register with the value corre- sponding to the length of the pulse if (olvl1=0 and olvl2=1). if olvl1=1 and olvl2=0 the length of the pulse is the difference between the oc2r and oc1r registers. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: C t = desired output compare period (seconds) C intclk = internal clock frequency C cc1-cc0 = timer clock prescaler the output compare 2 event causes the counter to be initialized to fffch (see figure 62 ). note: after a write instruction to the oc i hr regis- ter, the output compare function is inhibited until the oc i lr register is also written. the ocf1 and ocf2 bits cannot be set by hard- ware in pwm mode therefore the output compare interrupt is inhibited. the input capture interrupts are available. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. figure 62. pulse width modulation mode timing oc i r value = t * intclk cc[1:0] - 5 counter counter is reset to fffch ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter 34e2 fffc fffd fffe 2ed0 2ed1 2ed2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 9
106/179 st92141 - extended function timer (eft) extended function timer (contd) 7.3.4 interrupt management the interrupts of the extended function timer are mapped on the eight external interrupt channels of the microcontroller (refer to the interrupts chap- ter). depending on device specification, one of the fol- lowing configurations can occur: C the three interrupt sources are mapped on three different interrupt channels (to use this feature, the eftis bit must be reset) C the three interrupt sources are mapped on the same interrupt channel (to use this feature, the eftis bit must be set) each external interrupt channel has: C a trigger control bit in the eitr register (r242 - page 0) C a pending bit in the eipr register (r243 - page 0) C a mask bit in the eimr register (r244 - page 0) program the interrupt priority level using the eiplr register (r245 - page 0). for a description of these registers refer to the interrupts and dma chapters. use of three interrupt channels to use the interrupt features, for each interrupt channel used, perform the following sequence: C set the priority level of the interrupt channel(s) used for the extended function timer (eiprl register) C select the interrupt trigger edge(s) as rising edge (set the corresponding bit(s) in the eitr register) C set the ocis and/or icis and/or tois bit(s) of the cr3 register to select the peripheral interrupt source(s) C set the ocie and/or icie and/or toie bit(s) of the cr1 register to enable the peripheral to per- form interrupt requests on the desiderate events C in the eipr register, reset the pending bit(s) of the interrupt channels used by the peripheral in- terrupts to avoid any spurious interrupt requests being performed when the mask bit(s) is/are set C set the mask bit(s) of the interrupt channel(s) used to enable the mcu to acknowledge the in- terrupt requests of the peripheral. use of one external interrupt channel for all the interrupts to use the interrupt features, perform the following sequence: C set the priority level of the interrupt channel used (eiprl register) C select the interrupt trigger edge as rising edge (set the corresponding bit in the eitr register) C set the eftis bit of the cr3 register to select the peripheral interrupt sources C set the ocie and/or icie and/or toie bit(s) of the cr1 register to enable the peripheral to per- form interrupt requests on the wanted events C in the eipr register, reset the pending bit of the interrupt channel used by the peripheral inter- rupts to avoid any spurious interrupt requests be- ing performed when the mask bits is set C set the mask bits of the interrupt channels used to enable the mcu to acknowledge the interrupt requests of the peripheral. caution: care should be taken when using only one of the input capture pins, as both capture in- terrupts are enabled by the icie bit in the cr1 reg- ister. if only icap1 is used (for example), an inter- rupt can still be generated by the icap2 pin when this pin toggles, even if it is configured as a stand- ard output. if this case, the interrupt capture status bits in the sr register should handled in polling mode. caution: 1. it is mandatory to clear all eft interrupt flags simultaneously at least once before exiting an eft timer interrupt routine (the sr register must = 00h at some point during the interrupt routine), otherwise no interrupts can be issued on that channel anymore. refer to the following assembly code for an interrupt sequence example. 2. since a loop statement is needed inside the it routine, the user must avoid situations where an interrupt event period is narrower than the duration of the interrupt treatment. otherwise nested interrupt mode must be used to serve higher priority requests. 9
107/179 st92141 - extended function timer (eft) extended function timer (contd) note: a single access (read/write) to the sr regis- ter at the beginning of the interrupt routine is the first step needed to clear all the eft interrupt flags. in a second step, the lower bytes of the data registers must be accessed if the corresponding flag is set. it is not necessary to access the sr register between these instructions, but it can done. ; interrupt routine example push r234 ; save current page spp #28 ; set eft page l6: cp r254,#0 ; while e0_sr is not cleared jxz l7 tm r254,#128 ; check input capture 1 flag jxz l2 ; else go to next test ld r1,r241 ; dummy read to clear ic1lr ; insert your code here l2: tm r254,#16 ; check input capture 2 flag jxz l3 ; else go to next test ld r1,r243 ; dummy read to clear ic2lr ; insert your code here l3: tm r254,#64 ; check input compare 1 flag jxz l4 ; else go to next test ld r1,r249 ; dummy read to clear oc1lr ; insert your code here l4: tm r254,#8 ; check input compare 2 flag jxz l5 ; else go to next test ld r1,r251 ; dummy read to clear oc1lr ; insert your code here l5: tm r254,#32 ; check input overflow flag jxz l6 ; else go to next test ld r1,r245 ; dummy read to clear overflow flag ; insert your code here jx l6 l7: pop r234 ; restore current page iret 9
108/179 st92141 - extended function timer (eft) extended function timer (contd) 7.3.5 register description each timer is associated with three control and one status registers, and with six pairs of data reg- isters (16-bit values) relating to the two input cap- tures, the two output compares, the counter and the alternate counter. notes: 1. in the register description on the following pag- es, register and page numbers are given using the example of timer 0. on devices with more than one timer, refer to the device register map for the adresses and page numbers. 2. to work correctly with register pairs, it is strong- ly recommended to use single byte instructions. do not use word instructions to access any of the 16-bit registers. input capture 1 high register (ic1hr) r240 - read only register page: 28 reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) r241 - read only register page: 28 reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). input capture 2 high register (ic2hr) r242 - read only register page: 28 reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) r243 - read only register page: 28 reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 9
109/179 st92141 - extended function timer (eft) extended function timer (contd) counter high register (chr) r244 - read only register page: 28 reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) r245 - read/write register page: 28 reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) r246 - read only register page: 28 reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) r247 - read/write register page: 28 reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 9
110/179 st92141 - extended function timer (eft) extended function timer (contd) output compare 1 high register (oc1hr) r248 - read/write register page: 28 reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) r249 - read/write register page: 28 reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. output compare 2 high register (oc2hr) r250 - read/write register page: 28 reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) r251 - read/write register page: 28 reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 9
111/179 st92141 - extended function timer (eft) extended function timer (contd) control register 1 (cr1) r252 - read/write register page: 28 reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. 0: no effect. 1: forces the olvl2 bit to be copied to the ocmp2 pin. bit 3 = folv1 forced output compare 1. 0: no effect. 1: forces olvl1 to be copied to the ocmp1 pin. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and oc2e is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 9
112/179 st92141 - extended function timer (eft) extended function timer (contd) control register 2 (cr2) r253 - read/write register page: 28 reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 enable. 0: output compare 1 function is enabled, but the ocmp1 pin is a general i/o. 1: output compare 1 function is enabled, the ocmp1 pin is dedicated to the output compare 1 capability of the timer. bit 6 = oc2e output compare 2 enable. 0: output compare 2 function is enabled, but the ocmp2 pin is a general i/o. 1: output compare 2 function is enabled, the ocmp2 pin is dedicated to the output compare 2 capability of the timer. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc[1:0] clock control. the value of the timer clock depends on these bits: table 22. clock control bits bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the free running counter. 0: a falling edge triggers the free running counter. 1: a rising edge triggers the free running counter. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg cc1 cc0 timer clock 00 intclk / 4 01 intclk / 2 10 intclk / 8 11 external clock (where available) 9
113/179 st92141 - extended function timer (eft) extended function timer (contd) status register (sr) r254 - read only register page: 28 reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2-0 = reserved, forced by hardware to 0. control register 3 (cr3) r255 - read/write register page: 28 reset value: 0000 0000 (00h) bit 7-4 = unused read as 0. bit 3 = tois timer overflow interrupt selection. 0: select external interrupt. 1: select timer overflow interrupt. bit 2 = ocis output compare interrupt selection. 0: select external interrupt. 1: select timer output compare interrupt. bit 1 = icis input capture interrupt selection. 0: select external interrupt. 1: select timer input capture interrupt. bit 0 = eftis global timer interrupt selection. 0: select external interrupt. 1: select global timer interrupt. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 0 0 0 0 tois ocis icis eftis 9
114/179 st92141 - extended function timer (eft) extended function timer (contd) table 23. extended function timer register map address (dec.) register name 76543210 r240 ic1hr reset value msb xxxxxxx lsb x r241 ic1lr reset value msb xxxxxxx lsb x r242 ic2hr reset value msb xxxxxxx lsb x r243 ic2lr reset value msb xxxxxxx lsb x r244 chr reset value msb 1111111 lsb 1 r245 clr reset value msb 1111110 lsb 0 r246 achr reset value msb 1111111 lsb 1 r247 aclr reset value msb 1111110 lsb 0 r248 oc1hr reset value msb 1000000 lsb 0 r249 oc1lr reset value msb 0000000 lsb 0 r250 oc2hr reset value msb 1000000 lsb 0 r251 oc2lr reset value msb 0000000 lsb 0 r252 cr1 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 r253 cr2 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 r254 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 0 0 0 0 0 0 r255 cr3 reset value 0 0 0 0 0 0 0 0 tois 0 ocis 0 icis 0 eftis 0 9
115/179 st92141 - extended function timer (eft) extended function timer (contd) table 24. extended function timer page map timer number page (hex) eft0 1c 9
116/179 st92141 - 3-phase induction motor controller (imc) 7.4 3-phase induction motor controller (imc) 7.4.1 introduction the imc controller is designed for variable speed motor control applications. three pwm outputs are available for controlling a three-phase motor drive. rotor speed feedback is provided by captur- ing a tachogenerator input signal. 7.4.2 main features n 10-bit pwm up/down counter n classical and zerocentered pwm operating modes n full-scale pwm generation n 6-bit dead time generator n rotor speed measurement n 8 interrupt sources + 1 nmi 7.4.3 functional description the imc controller consists of the following func- tion blocks: C input and output pins C rotor speed measurement C 3-phase pwm signal generation C 6-bit dead time generation C polarity selection C interrupt generation the block diagram is shown in figure 63 . figure 63. imc controller block diagram 10-bit pwm counter 11-bit compare u reg. 11-bit preload compare u reg. 11-bit compare v reg. 11-bit preload compare v reg. 11-bit compare w reg. 11-bit preload compare w reg. 10-bit preload compare 0 reg. 10-bit compare 0 reg. dead time generator dead time generator reg. polarity selection & output registers 8-bit repetition down-counter 8-bit repetition counter reg. pwm counter prescaler reg. 8-bit prescaler 16-bit tacho counter 16-bit tacho capture reg. tacho prescaler reg. 12-bit prescaler div 2 otc int. cpt int. cm0 int. zpc int. zpc int. adt int. intclk cms bit cpc bit cpt=0 cpt=0 tacho uh ul clr on cpt ovf cpu int. cpv int. cpw int. dead time generator dead time generator vh vl wh wl 8-bit tacho compare reg. nmi nmi int. nmi control logic nmie bit nmil bit 9
117/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) 7.4.3.1 input and output pins C input pin tacho: signal input from a tachogenerator for measuring the rotor speed. nmi: input signal for disabling the imc output and sending an interrupt request to the st9 core. C output pins uh, ul, vh, vl, wh, wl: 3-phase pwm sig- nals and complementary signals (dedicated pins, refer to device pin description). note: the intclk signal is the internal clock of the st9 microcontroller (system clock). 7.4.3.2 rotor speed measurement the tacho signal is input from a schmitt trigger port. when a rising and/or falling edge occurs (pro- grammable edge sensitivity), the imc controller does the following: C captures the 16-bit tacho counter C clears the tacho counter (if ccpt bit is set) C generates a cpt interrupt the 16-bit tacho counter clock is derived from the clock used by the pwm counter, through a 12-bit prescaler. the 12-bit prescaler divides by 1, 2, 3, ......, 4096. if no edge occurs on the tacho signal or the event sensitivity is disabled (see table 25 ) and the 16-bit counter is running, an otc overflow inter- rupt will be issued when the msb (most significant byte) of the tacho counter reaches the tacho compare register value. 7.4.3.3 three-phase pwm generator the 3-phase pwm signal is generated using a 10- bit pwm counter and three 11-bit compare regis- ters one for each phase (u, v, w). the 10-bit pwm counter clock is supplied through a 8-bit prescaler (dividing by 1, 2, 3, .., 256). it can work in zerocentered mode or in classical mode. the mode is selected by the cms bit in the pcr0 register: zerocentered mode in this operating mode, the pwm counter counts up to the value loaded in the 10-bit compare 0 reg- ister then counts down until it reaches zero and re- starts counting up. classical mode in this operating mode, the pwm counter counts up to the value loaded in the 10-bit compare reg- ister. then the pwm counter is cleared and it re- starts counting up. figure 64 shows the counting sequence in classi- cal and zerocentered mode. pwm signal generation in zerocentered mode in this mode, all three pwm signals are set to 0 when the pwm counter reaches, in up-counting, the corresponding 11-bit compare register value and they are set to 1 when the pwm counter reaches the 11-bit compare value again in down- counting. the comparison is performed between the pwm counter value extended to 11 bits and the 11-bit compare register (either in zerocentered or in classical mode). figure 64. counting sequence in zerocentered and classical mode zerocentered mode 0 1 2 .... 15 16 15 .... 2 1 0 1 t classical mode 0 1 2 ..... 15 16 0 1 ..... 16 0 1 t t = pwm period, value of 10-bit compare register= 16 9
118/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) if the 11-bit compare register value is greater than the extended compare 0 register (the 11 th bit is set to 0), the corresponding pwm output signal is held at 1. if the 11-bit compare register value is 0, the corre- sponding pwm output signal is held at 0. figure 65 shows some zerocentered pwm wave- forms in an example where the compare 0 register value = 8. figure 65. zerocentered pwm waveforms (compare 0 register = 8) 012345678765432101 1 2 3 1 4 0 1 compare register value = 4 2 compare register value = 7 3 compare register value > = 8 4 compare register value = 0 9
119/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) pwm signals generation in classical mode in this mode, each of the three pwm signals set to 0 when the pwm counter reaches, in up-count- ing, the corresponding 11-bit compare register value and they are set to 1 when the pwm coun- ter is cleared. if the 11-bit compare register value is greater than the extended compare 0 register (the 11 th bit is set to 0), the corresponding pwm output signal is held at 1. if the 11-bit compare register value = 0, the corre- sponding pwm output signal is held at 0. figure 66 shows some classical pwm waves in an example where the compare 0 register value = 8. figure 66. classical pwm waveforms (compare 0 register = 8) 01234567801 1 2 3 1 4 0 1 compare register value = 4 2 compare register value = 8 3 compare register value > 8 4 compare register value = 0 9
120/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) repetition down-counter both in zerocentered and classical working mode, the four compare registers (one compare 0 and three for the u, v and w phases) are updated when the pwm counter value is zero and the 8-bit repetition down-counter has reached zero value by counting or by software programming (see pcr2 register). this means that data transits from the preload compare registers to the compare registers every n cycles of the pwm counter, where n is the val- ue of the 8-bit repetition register (n=1, 2, .., 256). 7.4.3.4 dead time generator for each phase there is one 6-bit dead time gen- erator. it generates two output signals: h and l. the h output signal is the same as the input phase signal except for the rising edge, which is delayed relatively to the input signal rising edge. the l output signal is the opposite of the input phase signal except the rising edge which is de- layed relatively to the input signal falling edge. the delay is the same for each phase (u, v, w) and its value is: delay = t x n where t is the period of the dead time generator input clock (intclk divided by 2) and n is the 6- bit number in the dead time register. if the dte bit in pcr0 register is reset, the dead time generator is disabled. this means that no delays are added to the l complemented outputs. figure 67 shows an example waveform of the u phase. if the delay is greater than the width of the active phase (l or h) then the corresponding pulse is not generated. see figure 68 and figure 69 . figure 67. dead time waveforms u uh ul delay delay 5v 5v 5v 0v 0v 0v 9
121/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) figure 68. dead time waveforms with delay greater than the negative pwm pulse figure 69. dead time waveforms with delay greater than the positive pwm pulse u uh ul delay 5v 5v 5v 0v 0v 0v u uh ul delay 5v 5v 5v 0v 0v 0v 9
122/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) 7.4.3.5 polarity selection the polarity selection performs a logical comple- ment of the input signals (uh, ul, vh, vl, wh, wl) as programmed in the polarity selection register. 7.4.3.6 interrupts the imc controller generates 8 interrupt requests and 1 nmi. each interrupt request has a separate vector address. the nmi interrupt is managed by the st9 as a top level interrupt.the interrupt pri- ority is fixed by hardware as listed below: 7.4.4 tacho counter operating mode the tacho counter can work in one shot mode or in continuous mode. in both continuous or one shot mode the capture event can be generated by hardware (tacho pin) or by software (stc bit in the pcr1 register) ac- cording to the value of the tes bit in the pcr1 register. when the ctc bit in the pcr0 register is set, the tacho counter is cleared (this bit is reset by hardware). 7.4.4.1 tacho counter in one shot mode in this operating mode (tcb bit = 1 in the pcr1 register) the counter does the following: C counting is started by setting the tce bit in the pcr0 register. C when a capture event occurs, counting is stopped (tce bit is cleared), the value is cap- tured and a cpt interrupt is generated (if the ccpt bit in the pcr1 register is set, the counter is cleared). C when the msb of tacho counter reaches the tacho compare register value, the counter is stopped (tce bit is cleared) and the otc inter- rupt is generated. 7.4.4.2 tacho counter in continuous mode in this operating mode (tcb bit = 0 in the pcr1 register) the counter does the following: C counting is started by setting the tce bit in the pcr0 register. C every capture event, the value is captured and a cpt interrupt is generated (if the ccpt bit in the pcr1 register is set, the counter is cleared). C when the msb of tacho counter reaches the tacho compare register value, an otc interrupt is generated. 7.4.5 imc operating mode the imc controller can work in two different modes: C hardware operating mode (dts bit = 0 in prcr2 register) C software operating mode (dts bit = 1 in prcr2 register) in both modes, when the corresponding event oc- curs, the adt and the other interrupts are generat- ed. when the cpc bit in the pcr0 register is set, the pwm counter is cleared (this bit is reset by soft- ware). 7.4.5.1 imc hardware operating mode after system reset, the compare u, v, w and compare 0 register values are all 0. when the pwm counter is enabled (by setting the pce bit in the pcr0 register) and every time the repetition counter and the pwm counter reach 0 value, the repetition counter is loaded, the preload registers are loaded into the compare reg- isters and an adt interrupt is generated. note: if an adt (or any other interrupt) is generat- ed and the previous one is not completed, the last one will be lost without any error condition being issued. priority interrupt source cpu top level int. priority nmi: event on external pin 0 high priority adt: data transfer (when data is trans- ferred from the preload registers to the compare registers) 1 zpc: pwm counter zero event 2 cm0: pwm counter compare 0 event 3 cpt: tacho counter capture event 4 cpu: compare u event (pwm counter reached u compare value) 5 cpv: compare v event (pwm counter reached v compare value) 6 cpw: compare w event (pwm coun- ter reached w compare value) 7 low priority otc: tacho counter overflow 9
123/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) 7.4.5.2 imc software operating mode in this operating mode, the repetition register and any compare register can be independently up- dated by software by setting the sdt bit in the pcr2 register (this bit will be reset by hardware) and the corresponding enable bit in the same reg- ister. no hardware loading is performed when an adt interrupt is generated. note: the repetition counter is decremented im- mediately when the repetition counter is updated. 7.4.6 imc output selection the imc output can be selected from the following sources: C opr register (bit 5:0), by setting the ods bit in the opr register. C dead time generator outputs, by setting the odcs bit in pcr0 register. C pwm counter outputs (h and l) are not comple- mented when the odcs bit is reset. figure 70 shows the imc output selection. figure 70. imc output selection. 0 1 0 1 uh ul vh vl wh wl pwm counter dead time ods bit odcs bit polarity selection generator opr register psr register 9
124/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) 7.4.7 nmi management figure 71 shows how the external input nmi signal is managed by the imc peripheral. after an st9 reset, the nmie bit in the pcr1 reg- ister is cleared, which means that nmi signal com- ing from the external pin is sent, as is, to the st9 core without affecting the imc peripheral. if the nmie bit is set, when an nmi event occurs on the external pin, it will be acknowledged (de- pending on the value of the nmil bit in the psr register). in this case: C the nmi bit in the imcivr register is set C the dedicated output pins of the imc are put in high impedance C a high level signal is sent to the st9 top level interrupt C the ope bit is cleared (as the nmi interrupt sig- nal is no longer active) notes : 1. because the signal to the st9 top level interrupt is active high, the tltev bit in the eivr register must be set. 2. when the user wants to leave the nmi interrupt routine, it is strongly recommended to verify, be- fore leaving the routine, that the nmi pending bit (bit 3 of imcivr) is really at 0. to do this, the user can try to write the nmi pending bit to 0 re- peatedly until it has successfully been cleared. the nmi pending bit in imcivr register can be written to 0 only if the external nmi signal is no longer active. this makes sure that no nmi event will be lost. if the user leaves the nmi interrupt rou- tine without clearing the nmi pending bit, no other nmi interrupt can be issued afterwards because the st9 top level interrupt is edge sensitive. figure 71. nmi management by the imc peripheral 0 1 nmie bit nmi bit level selection nmil bit nmi to st9 core nmi from ext pin 9
125/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) 7.4.8 register description tacho capture register high (tcpth) r240 - read only register page: 51 reset value: undefined bit 7:0 = tch[7:0] most significant byte of tacho capture register. tacho capture register low (tcptl) r241 - read only register page: 51 reset value: undefined bit 7:0 = tcl[7:0] low byte of tacho capture reg- ister. tacho compare register (tcmp) r242 - read/write register page: 51 reset value: 1111 1111 (ffh) bit 7:0 = tcm[7:0] byte of tacho compare regis- ter. when the most significant byte of the tacho counter reaches tcmp value, the tacho counter is cleared and an otc interrupt is generated both in continuous and one shot mode. 70 tch7 tch6 tch5 tch4 tch3 tch2 tch1 tch0 70 tcl7 tcl6 tcl5 tcl4 tcl3 tcl2 tcl1 tcl0 70 tcm7 tcm6 tcm5 tcm4 tcm3 tcm2 tcm1 tcm0 9
126/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) interrupt pending register (ipr) r243 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7 = cm0: compare 0 of pwm pending bit. this bit is set by hardware when the pwm counter reaches the value in the compare 0 register while cm0e=1. the cm0 bit must be cleared by soft- ware. 0: no cmp0 interrupt occurred 1: cmp0 interrupt pending bit 6 = cpt: capture of tacho counter pending bit . this bit is set by hardware when a tacho signal event occurs while cpte=1. the cpt bit must be cleared by software. 0: no cpt interrupt occurred 1: cpt interrupt pending bit 5 = otc: overflow of tacho counter pending bit. this bit is set by hardware on a tacho counter overflow while otce=1. the otc bit must be cleared by software. 0: no otc interrupt occurred 1: otc interrupt pending bit 4 = adt: automatic data transfer pending bit. this bit is set by hardware when data is trans- ferred from the preload registers to the compare registers while adte=1. the adt bit must be cleared by software. 0: no adt interrupt occurred 1: adt interrupt pending bit 3 = zpc: zero of pwm counter pending bit. this bit is set by hardware when the pwm counter reaches zero while zpce=1. the zpc bit must be cleared by software. 0: no zpc interrupt occurred 1: zpc interrupt pending bit 2 = cpu: compare u pending bit. in classical mode (cms bit = 0), this bit is set by hardware when the pwm counter reaches the compare u register value while cpue=1. in zerocentered mode (cms bit =1), this bit is set by hardware when the pwm counter reaches the compare u register value while cpue=1 in up or downcounting (depending on the udis bit in the psr register). the cpu bit must be cleared by software. 0: no cpu interrupt occurred 1: cpu interrupt pending bit 1 = cpv: compare v pending bit. in classical mode (cms bit = 0), this bit is set by hardware when the pwm counter reaches the compare v register value while cpve=1. in zerocentered mode (cms bit =1), this bit is set by hardware when the pwm counter reaches the compare v register value while cpve=1 in up or downcounting (depending on the udis bit in the psr register). the cpprs register). the cpv bit must be cleared by software. 0: no cpv interrupt occurred 1: cpv interrupt pending bit 0 = cpw: compare w pending bit. in classical mode (cms bit = 0), this bit is set by hardware when the pwm counter reaches the compare w register value while cpwe=1. in zerocentered mode (cms bit =1), this bit is set by hardware when the pwm counter reaches the compare w register value while cpwe=1 in up or downcounting (depending on the udis bit in the psr register). the cpw bit must be cleared by software. 0: no cpw interrupt occurred 1: cpw interrupt pending note 1: none of the bits in the ipr register can be set by software, they can only be cleared. note 2: to clear the bits in the ipr register, the user must not use direct addressing bit instruc- tions such as and, or, bres, etc. because some interrupts may not be generated as expected. to avoid this, do the following: to clear one pending bit of the ipr register, load the register with the mask corresponding to the bit to be cleared. for example: to clear the cpw bit, use the instruction ld r243,#1111 1110 rather than the instruction and r243,#1111 1110. 70 cm0 cpt otc adt zpc cpu cpv cpw 9
127/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) tacho prescaler register high (tprsh) r244 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:4 = reserved. bit 3:0 = tprh[3:0] most significant bits of tacho prescaler value (n). tacho prescaler register low (tprsl) r245 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:0 = tprl[7:0] low byte of tacho prescaler value (n). if n = 0 tacho prescaler divides by 1. pwm counter prescaler register (cprs) r246 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:0 = cpr[7:0] pwm counter prescaler value (n) . this value divides the intclk frequency by (n +1), i.e. if n = 0, intclk is divided by 1. repetition counter register (rep) r247 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:0 = rep[7:0] repetition counter value (n). if n = 0, each time the pwm counter reaches ze- ro, the compare registers are updated and an adt interrupt is generated. 70 ---- tprh 3 tprh 2 tprh 1 tprh 0 70 tprl 7 tprl 6 tprl 5 tprl 4 tprl 3 tprl 2 tprl 1 tprl 0 70 cpr7 cpr6 cpr5 cpr4 cpr3 cpr2 cpr1 cpr0 70 rep7 rep6 rep5 rep4 rep3 rep2 rep1 rep0 9
128/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) compare phase w preload register high (cpwh) r248 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:0 = cpwh[7:0] most significant byte of phase w preload value compare phase w preload register low (cpwl) r249 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:5 = cpwl[7:5] low bits of phase w preload value . bit 4:0 = reserved. compare phase v preload register high (cpvh) r250 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:0 = cpvh[7:0] most significant byte of phase v preload value compare phase v preload register low (cpvl) r251 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:5 = cpvl[7:5] low bits of phase v preload value . bit 4:0 = reserved. 70 cpwh 7 cpwh 6 cpwh 5 cpwh 4 cpwh 3 cpwh 2 cpwh 1 cpwh 0 70 cpwl 7 cpwl 6 cpwl 5 ----- 70 cpvh7 cpvh6 cpvh5 cpvh4 cpvh3 cpvh2 cpvh1 cpvh0 70 cpvl7cpvl6cpvl5----- 9
129/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) compare phase u preload register high (cpuh) r252 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:0 = cpuh[7:0] most significant byte of phase u preload value compare phase u preload register low (cpul) r253 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:5 = cpul[7:5] low bits of phase u preload value . bit 4:0 = reserved. compare 0 preload register high (cp0h) r254 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:2 = reserved. bit 1:0 = cp0h[1:0] most significant bits of com- pare 0 preload value. compare 0 preload register low (cp0l) r255 - read/write register page: 51 reset value: 0000 0000 (00h) bit 7:0 = cp0l[7:0] low byte of compare 0 preload value . note: cp0[9:0] value must be greater than 1. 70 cpuh 7 cpuh 6 cpuh 5 cpuh 4 cpuh 3 cpuh 2 cpuh 1 cpuh 0 70 cpul7cpul6cpul5----- 70 - - - - - - cp0h1 cp0h0 70 cp0l7 cp0l6 cp0l5 cp0l4 cp0l3 cp0l2 cp0l1 cp0l0 9
130/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) peripheral control register 0 (pcr0) r248 - read/write register page: 48 reset value: 1000 0011 (83h) bit 7 = dte: dead time counter enable. 0: stop and bypass the dead time counter 1: enable the dead time counter bit 6 = tce: tacho counter enable. 0: stop tacho counter and prescaler 1: start tacho counter and prescaler note: this bit is reset by the counter overflow or by the tacho capture when the imc controller is in one shot mode. bit 5 = pce: pwm counter enable . 0: stop pwm counter and prescaler 1: start pwm counter and prescaler bit 4 = ctc: clear of tacho counter. 0: no effect 1: clear the tacho counter (this bit is reset by hardware) bit 3 = cpc: clear of pwm counter. 0: no effect. 1: clear the pwm counter (his bit is reset by hard- ware) bit 2 = cms: pwm counter mode selection. 0: classical mode. 1: zerocentered mode bit 1 = udcs: up/down - status (read only). this bit is set and cleared by hardware. 0: the pwm counter is counting down. 1: the pwm counter is counting up. bit 0 = odcs: output dead time counter selec- tion 0: select the same signal for both (h, l) outputs 1: select complementary signal for output (dead time generator outputs) peripheral control register 1 (pcr1) r249 - read/write register page: 48 reset value: 0000 0000 00h bit 7 = reserved. bit 6 = nmie: non maskable interrupt enable 0: when an nmi event occurs on the external pin, it is sent as is (independently of the nmil value) to the st9 core and has no effect on the imc controller. 1: when an nmi event occurs on the external pin, if it is acknowledged (depending on the nmil bit) an interrupt request is sent to the st9 core (a high level signal ), the nmi pending bit (nmi bit in imcivr register) is set and the ope bit is cleared. bit 5 = ccpt: clear on capture of tacho counter 0: no clear on capture 1: clear on capture bit 4 = tes: tacho event selection . 0: select capture by tacho event signal 1: select capture by software (stc bit) bit 3 = stc: software tacho capture 0: no effect 1: capture the tacho counter (while tes=1). this bit is reset by hardware bit 2 = tcb: tacho counter mode 0: select continuous mode. 1: select one shot mode (counting starts when tce bit is set and stops when a capture or an overflow event occurs). bit 1:0 = tin[1:0] tacho signal event sensitivity these bits select which tacho signal event trig- gers the tacho capture register. table 25. tacho signal event sensitivity 70 dte tce pce ctc cpc cms udcs odcs 70 - nmie ccpt tes stc tcb tin1 tin0 tin1 tin0 event 0 0 no operation 0 1 falling edge 1 0 rising edge 1 1 rising and falling edges 9
131/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd)) peripheral control register 2 (pcr2) r250 - read/write register page: 48 reset value: 0000 0000 (00h) bit 7 = gpie: global peripheral interrupt enable. 0: disable all imc controller interrupts. 1: enable all imc controller interrupts. bit 6 = rse: enable software data transfer to repetition register. 0: disable loading of repetition register by sdt bit 1: enable loading of repetition register by sdt bit bit 5 = cwse: enable software data transfer to compare w. 0: disable load of compare w register by sdt bit 1: enable load of compare w register by sdt bit bit 4 = cvse: enable software data transfer to compare v register. 0: disable loading of compare v register by sdt bit 1: enable loading of compare v register by sdt bit bit 3 = cuse: enable software data transfer to compare u register. 0: disable loading of compare u register by sdt bit 1: enable loading of compare u register by sdt bit bit 2 = c0se: enable software data transfer to compare 0 register. 0: disable loading of compare 0 register by sdt bit 1: enable loading of compare 0 register by sdt bit bit 1 = sdt: software data transfer 0: no effect 1: transfer data from preload to compare register (while dts=1) (this bit is reset by hardware). bit 0 = dts: data transfer mode selection. 0: hardware transfer using repetition counter 1: software transfer using sdt bit. polarity selection register (psr) r251 - read/write register page: 48 reset value: 0000 0000 (00h) bit 7 = nmil: non maskable interrupt level. 0: low level of nmi event is acknowledged. 1: high level of nmi event is acknowledged. bit 6 = udis: up-down interrupt select. when the pwm counter is working in zerocen- tered mode the meaning is: 0: the compare interrupts (cpu, cpv, cpw) are issued when the counter is counting up. 1: the compare interrupts (cpu, cpv, cpw) are issued when the counter is counting down. this bit has no effect when the counter is working in classical mode bit 5 = puh: polarity of uh phase. 0: positive logical level. 1: complemented logical level. bit 4 = pul: polarity of ul phase. 0: positive logical level. 1: complemented logical level. bit 3 = pvh: polarity of vh phase. 0: positive logical level. 1: complemented logical level. bit 2 = pvl: polarity of vl phase. 0: positive logical level. 1: complemented logical level. bit 1 = pwh: polarity of wh phase. 0: positive logical level. 1: complemented logical level. bit 0: pwl: polarity of wl phase. 0: positive logical level. 1: complemented logical level. 70 gpie rse cwse cvse cuse c0se sdt dts 70 nmil udis puh pul pvh pvl pwh pwl 9
132/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) output peripheral register (opr) r252 - read/write register page: 48 reset value: 0000 0000 (00h) bit 7 = ope: output port enable. this bit can be set by software only if the nmi bit is cleared. 0: output port is in high impedance (without pull- up and pull-down resistor). 1: output port is available for data transfer. bit 6 = ods: output data selection. 0: dead time generator data. 1: select the bit 5:0 data bit 5:0 = uh, ul, vh, vl, wh, wl phases these bits can be sent out through the output port. interrupt mask register (imr) r253 - read/write register page: 48 reset value: 0000 0000 (00h) bit 7 = cm0e: compare 0 of pwm counter enable. 0: disabled. 1: enabled. bit 6 = cpte: capture of tacho counter interrupt enable. 0: disabled. 1: enabled. bit 5 = otce: overflow of tacho counter interrupt enable. 0: disabled. 1: enabled. bit 4 = adte: automatic data transfer interrupt enable. 0: disabled. 1: enabled. bit 3 = zpce: zero of pwm counter interrupt ena- ble . 0: disabled. 1: enabled. bit 2:0 = cpue, cpve, cpwe: compare u, v, w interrupt enable . 0: disabled. 1: enabled. 70 ope ods uh ul vh vl wh wl 70 cm0e cpte otce adte zpce cpue cpve cpwe 9
133/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) dead time generator register (dtg) r254 - read/write register page: 48 reset value: 0011 1111 (3fh) bit 7:6 = reserved. bit 5:0 = dtg[5:0] dead time generator value (n) . the delay is n x intclk period multiplied by 2. if n = 0 the delay is 0. imc interrupt vector register (imcivr) r255 - read/write register page: 48 reset value: undefined (17h) bit 7:4 = v[3:0]: interrupt vector base address . user programmable interrupt vector bits. the most significant nibble of the interrupt vector address is given by v[3:0]. the other nibble is giv- en by w[3:0] where w[0] is forced to 0 and w[3:1] are set by hardware according to the table 26 in- terrupt source address . table 26. interrupt source address bit 3 = nmi: non maskable interrupt pending bit. this bit is set by hardware when an nmi event oc- curs and the nmie bit = 1. the nmi bit can be cleared by software. it cannot be set by software. as long as this bit is 1 the nmi signal to st9 is kept active (high level). 0: no nmi pending 1: nmi pending note: as long as the external nmi signal is active the nmi bit can not be reset. bit 2:0 = pl[2:0] : priority level for the peripheral interrupt. 70 - - dtg5 dtg4 dtg3 dtg2 dtg1 dtg0 70 v3 v2 v1 v0 nmi pl2 pl1 pl0 w[3:1] interrupt source 000 adt data transfer 001 zpc zero event of pwm counter 010 cm0 pwm counter compare 0 011 cpt tacho capture 100 cpu compare u 101 cpv compare v 110 cpw compare w 111 otc tacho counter overflow 9
134/179 st92141 - 3-phase induction motor controller (imc) induction motor controller (contd) table 27. imc controller register map page 51 register no. register name 76543210 r240 tcpth tch7 tch6 tch5 tch4 tch3 tch2 tch1 tch0 r241 tcptl tcl7 tcl6 tcl5 tcl4 tcl3 tcl2 tcl1 tcl0 r242 tcmp tcp7 tcp6 tcp5 tcp4 tcp3 tcp2 tcp1 tcp0 r243 ipr cm0 cpt otc adt zpc cpu cpv cpw r244 tprsh ----tph3 tph2 tph1 tph0 r245 tprsl tprl7 tprl6 tprl5 tprl4 tprl3 tprl2 tprl1 tprl0 r246 cprs cpr7 cpr6 cpr5 cpr4 cpr3 cpr2 cpr1 cpr0 r247 rep rep7 rep6 rep5 rep4 rep3 rep2 rep1 rep0 r248 cpwh cpwh7 cpwh6 cpwh5 cpwh4 cpwh3 cpwh2 cpwh1 cpwh0 r249 cpwl cpwl7cpwl6cpwl5----- r250 cpvh cpvh7 cpvh6 cpvh5 cpvh4 cpvh3 cpvh2 cpvh1 cpvh0 r251 cpvl cpvl7cpvl6cpvl5----- r252 cpuh cpuh7 cpuh6 cpuh5 cpuh4 cpuh3 cpuh2 cpuh1 cpuh0 r253 cpul cpu7lcpul6cpul5----- r254 cp0h ------cp0h1cp0h0 r255 cp0l cp0l7 cp0l6 cp0l5 cp0l4 cp0l3 cp0l2 cp0l1 cp0l0 page 48 register no. register name 76543210 r248 pcr0 dte tce pce ctc cpc cms udcs odcs r249 pcr1 - nmie ccpt tes stc tcb tin1 tin0 r250 pcr2 gpie rse cwse cvse cuse cose sdt dts r251 psr nmil udis puh pul pvh pvl pwh pwl r252 opr ope ods uh ul vh vl wh wl r253 imr cm0e cpte otce adte zpce cpue cpve cpwe r254 dtg - - dtg5 dtg4 dtg3 dtg2 dtg1 dtg0 r255 imcivr v3 v2 v1 v0 nmi pl2 pl1 pl0 9
135/179 st92141 - serial peripheral interface (spi) 7.5 serial peripheral interface (spi) 7.5.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 7.5.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n four master mode frequencies n maximum slave mode frequency = intclk/2. n fully programmable 3-bit prescaler for a wide range of baud rates, plus a programmable divider by 2 n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 7.5.3 general description the spi is connected to external devices through 4 alternate pins: C miso: master in slave out pin C mosi: master out slave in pin C sck: serial clock pin Css : slave select pin to use any of these alternate functions (input or output), the corresponding i/o port must be pro- grammed as alternate function output. a basic example of interconnections between a single master and a single slave is illustrated on figure 72 . the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. four possible data/clock timing relationships may be chosen (see figure 75 ) but master and slave must be programmed with the same timing mode. figure 72. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit 9
136/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) figure 73. serial peripheral interface block diagram dr read buffer 8-bit shift register write read internal bus spi spie spoe spis mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state cr sr - --- - it request master control prescaler /1 .. /8 prs0 prs1 prs2 pr st9 peripheral clock (intclk) ext. int 0 1 1/2 0 1 div2 9
137/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) 7.5.4 functional description figure 73 shows the serial peripheral interface (spi) block diagram. this interface contains 4 dedicated registers: C a control register (cr) C a prescaler register (pr) C a status register (sr) C a data register (dr) refer to the cr, pr, sr and dr registers in sec- tion 7.5.6for the bit definitions. 7.5.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure C define the serial clock baud rate by setting/re- setting the div2 bit of pr register, by writing a prescaler value in the pr register and pro- gramming the spr0 & spr1 bits in the cr register. C select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 75 ). Cthe ss pin must be connected to a high level signal during the complete byte transmit se- quence. C the mstr and spoe bits must be set (they remain set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten the dr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if the spis and spie bits are set. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a write or a read of the dr register. note: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. 9
138/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) 7.5.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the pr register and spr0 & spr1 bits in the cr is not used for the data transfer. procedure C for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). see figure 75 . Cthe ss pin must be connected to a low level signal during the complete byte transmit se- quence. C clear the mstr bit and set the spoe bit to assign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: C the spif bit is set by hardware C an interrupt is generated if the spis and spie bits are set. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set. 2. a write or a read of the dr register. notes: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 7.5.4.6). depending on the cpha bit, the ss pin has to be set to write to the dr register between each data byte transfer to avoid a write collision (see section 7.5.4.4). 9
139/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) 7.5.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 75 , shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the first clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 74 ). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the second clock transition. this pin must be toggled high and low between each byte transmitted (see figure 74 ). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its dr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the dr without producing a write collision. figure 74. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 9
140/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) figure 75. data clock timing diagram cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the control timing chapter. (from slave) 9
141/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) 7.5.4.4 write collision error a write collision occurs when the software tries to write to the dr register while a data transfer is tak- ing place with an external device. when this hap- pens, the transfer continues uninterrupted and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device dr register and output the msbit on to the exter- nal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the dr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the dr register without generating a write colli- sion. in master mode collision in the master device is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 76 ). figure 76. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1 st step read sr read dr write dr 2 nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1 st step 2 nd step wcol=0 before the 2 nd step read sr read dr note: writing in dr register in- stead of reading in it do not reset wcol bit read sr or then then then 9
142/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) 7.5.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: C the modf bit is set and an spi interrupt is generated if the spie bit is set. C the spoe bit is reset. this blocks all output from the device and disables the spi periph- eral. C the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the sr register while the modf bit is set. 2. a write to the cr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spoe and mstr bits may be restored to their original state during or after this clearing sequence. hardware does not allow the user to set the spoe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 7.5.4.6 overrun condition an overrun condition occurs, when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the dr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al. 9
143/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) 7.5.4.7 single master and multimaster configurations there are two types of spi systems: C single master system C multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 77 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its dr regis- ter. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the cr register and the modf bit in the sr register. figure 77. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu 9
144/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) 7.5.5 interrupt management the interrupt of the serial peripheral interface is mapped on one of the eight external interrupt channels of the microcontroller (refer to the inter- rupts chapter). each external interrupt channel has: C a trigger control bit in the eitr register (r242 - page 0), C a pending bit in the eipr register (r243 - page0), C a mask bit in the eimr register (r244 - page 0). program the interrupt priority level using the ei- plr register (r245 - page 0). for a description of these registers refer to the interrupts and dma chapters. to use the interrupt feature, perform the following sequence: C set the priority level of the interrupt channel used for the spi (eiprl register) C select the interrupt trigger edge as rising edge (set the corresponding bit in the eitr register) C set the spis bit of the cr register to select the peripheral interrupt source C set the spie bit of the cr register to enable the peripheral to perform interrupt requests C in the eipr register, reset the pending bit of the interrupt channel used by the spi interrupt to avoid any spurious interrupt requests being per- formed when the mask bit is set C set the mask bit of the interrupt channel used to enable the mcu to acknowledge the interrupt re- quests of the peripheral. note : in the interrupt routine, reset the related pending bit to avoid the interrupt request that was just acknowledged being proposed again. then, after resetting the pending bit and before the iret instruction, check if the spif and modf interrupt flags in the sr register) are reset; other- wise jump to the beginning of the routine. if, on re- turn from an interrupt routine, the pending bit is re- set while one of the interrupt flags is set, no inter- rupt is performed on that channel until the flags are set. a new interrupt request is performed only when a flag is set with the other not set. 7.5.5.1 register map depending on the device, one or two serial pe- ripheral interfaces can be present. the previous table summarizes the position of the registers of the two peripherals in the register map of the mi- crocontroller. address page name spi0 r240 (f0h) 7 dr0 r241 (f1h) 7 cr0 r242 (f2h) 7 sr0 r243 (f3h) 7 pr0 spi1 r248 (f8h) 7 dr1 r249 (f9h) 7 cr1 r250 (fah) 7 sr1 r251 (fbh) 7 pr1 9
145/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) 7.5.6 register description data register (spdr) r240 - read/write register page: 7 reset value: 0000 0000 (00h) the dr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data register, the buffer is ac- tually being read. warning: a write to the dr register places data di- rectly into the shift register for transmission. a read to the dr register returns the value located in the buffer and not the content of the shift regis- ter (see figure 73 ). control register (spcr) r241 - read/write register page: 7 reset value: 0000 0000 (00h) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever either spif or modf are set in the sr register while the other flag is 0. bit 6 = spoe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 7.5.4.5 master mode fault ). 0: spi alternate functions disabled (miso, mosi and sck can only work as input) 1: spi alternate functions enabled (miso, mosi and sck can work as input or output depending on the value of mstr) note: to use the miso, mosi and sck alternate functions (input or output), the corresponding i/o port must be programmed as alternate function output. bit 5 = spis interrupt selection. this bit is set and cleared by software. 0: interrupt source is external interrupt 1: interrupt source is spi bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 7.5.4.5 master mode fault ). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1:0 = spr[1 : 0] serial peripheral rate. these bits are set and cleared by software. they select one of four baud rates to be used as the se- rial clock when the device is a master. these 2 bits have no effect in slave mode. table 28. serial peripheral baud rate 70 d7 d6 d5 d4 d3 d2 d1 d0 70 spie spoe spis mstr cpol cpha spr1 spr0 intclk clock divide spr1 spr0 200 401 16 1 0 32 1 1 9
146/179 st92141 - serial peripheral interface (spi) serial peripheral interface (contd) status register (spsr) r242 - read only register page: 7 reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the cr register. it is cleared by a soft- ware sequence (an access to the sr register fol- lowed by a read or write to the dr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the dr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the dr register is done during a transmit sequence. it is cleared by a software sequence (see figure 76 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 7.5.4.5 master mode fault ). an spi interrupt can be gen- erated if spie=1 in the cr register. this bit is cleared by a software sequence (an access to the sr register while modf=1 followed by a write to the cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3:0 = unused. prescaler register (sppr) r243 - read/write register page: 7 reset value: 0000 0000 (00h) bits 7:5 = reserved, forced by hardware to 0 . bit 4 = div2 divider enable. this bit is set and cleared by software. 0: divider by 2 enabled. 1: divider by 2 disabled. bit 3 = reserved. forced by hardware to 0. bits 2:0 = prs[2:0] prescaler value. these bits are set and cleared by software. the baud rate generator is driven by intclk/(n1*n2*n3) where n1= prs[2:0]+1, n2 is the value of the spr[1:0] bits, n3 = 1 if div2=1 and n3= 2 if div2=0. refer to figure 73 . these bits have no effect in slave mode. table 29. prescaler baud rate 70 spifwcol-modf---- 70 0 0 0 div2 0 prs2 prs1 prs0 prescaler division factor prs2 prs1 prs0 1 (no division) 0 0 0 2001 ... 8111 9
147/179 st92141 - analog to digital converter (adc) 7.6 analog to digital converter (adc) important note: this chapter is a generic descrip- tion of the adc peripheral. however depending on the st9 device, some or all of the interface signals described may not be connected to external pins. for the list of adc pins present on the st9 device, refer to the device pinout description in the first section of the data sheet. 7.6.1 introduction the analog to digital converter (adc) comprises an input multiplex channel selector feeding a suc- cessive approximation converter. the conversion time depends on the intclk fre- quency and the prescaler factor stored in the pr[2:0] bits of the crr register (r252). the minimum conversion time is 138 intclk and with the maximum prescaling factor it becomes about 16 times longer. for instance, with intclk at 20 mhz and pr[2:0] equal to "111", conversion of the selected channel requires 6.9s. it requires 27.45s if pr[2:0] equals "110" and so on. refer to table 30 for the list of conversion and sampling times. the 6.9s time includes the 4 m s required by the built-in sample and hold circuitry, which minimiz- es the need for external components and allows quick sampling of the signal to minimise warping and conversion error. conversion resolution is 8 bits, with 1 lsb maxi- mum error in the input range between v ss and the analog v dd reference. the converter uses a fully differential analog input configuration for the best noise immunity and pre- cision performance. two separate supply refer- ences are provided to ensure the best possible supply noise rejection. in fact, the converted digital value, is referred to the analog reference voltage which determines the full scale converted value. naturally , analog and digital v ss must be com- mon. if analog supplies are not present, input ref- erence voltages are referred to the digital ground and supply. up to 8 multiplexed analog inputs are available, depending on the specific device type. a group of signals can be converted sequentially by simply programming the starting address of the first ana- log channel to be converted and with the auto- scan feature. two analog watchdogs are provided, allowing continuous hardware monitoring of two input chan- nels. an interrupt request is generated whenever the converted value of either of these two analog inputs is outside the upper or lower programmed threshold values. the comparison result is stored in a dedicated register. figure 78. block diagram interrupt unit int. vector pointer int. control register compare result register threshold register threshold register threshold register threshold register 7u 7l 6u 6l compare logic data register 7 data register 6 data register 5 data register 4 data register 3 data register 2 data register 1 data register 0 successive approximation a/d converter analog mux ain 7 ain 6 ain 5 ain 4 ain 3 ain 2 ain 1 ain 0 conversion result autoscan logic control reg. control logic internal trigger external trigger va00223 9
148/179 st92141 - analog to d igital converter (adc) analog to digital converter (contd) single and continuous conversion modes are available. conversion may be triggered by an ex- ternal signal or, internally, by the multifunction timer. conversion time the maximum conversion time is as follows: 138 * fdf * intclk the minimum sample time is: 84 * fdf * intclk where fdf is the frequency division factor (refer to the pr bit description in the ccr register). for instance, if pr[2:0] = 100 -> fdf = 8 then the conversion time is: 138 * 8 * intclk = 1104 and the sample time is 84 * 8 * intclk = 672 intclk. a power-down programmable bit allows the adc to be set in low-power idle mode. the adcs interrupt unit provides two maskable channels (analog watchdog and end of conver- sion) with hardware fixed priority, and up to 7 pro- grammable priority levels. caution : adc input pin configuration the input analog channel is selected by using the i/o pin alternate function setting (pxc2, pxc1, pxc0 = 1,1,1) as described in the i/o ports sec- tion. the i/o pin configuration of the port connect- ed to the a/d converter is modified in order to pre- vent the analog voltage present on the i/o pin from causing high power dissipation across the input buffer. deselected analog channels should also be maintained in alternate function configuration for the same reason. 7.6.2 functional description 7.6.2.1 operating modes two operating modes are available: continuous mode and single mode. to enter one of these modes it is necessary to program the cont bit of the control logic register. the continuous mode is selected when cont is set, while single mode is selected when cont is reset. both modes operate in autoscan configuration, allowing sequential conversion of the input chan- nels. the number of analog inputs to be converted may be set by software, by setting the number of the first channel to be converted into the control register (sc2, sc1, sc0 bits). as each conver- sion is completed, the channel number is automat- ically incremented, up to channel 7. for example, if sc2, sc1, sc0 are set to 0,1,1, conversion will proceed from channel 3 to channel 7, whereas, if sc2, sc1, sc0 are set to 1,1,1, only channel 7 will be converted. when the st bit of the control logic register is set, either by software or by hardware (by an inter- nal or external synchronisation trigger signal), the analog inputs are sequentially converted (from the first selected channel up to channel 7) and the re- sults are stored in the relevant data registers. in single mode (cont = 0), the st bit is reset by hardware following conversion of channel 7; an end of conversion (ecv) interrupt request is is- sued and the adc waits for a new start event. in continuous mode (cont = 1), a continuous conversion flow is initiated by the start event. when conversion of channel 7 is complete, con- version of channel 's' is initiated (where 's' is spec- ified by the setting of the sc2, sc1 and sc0 bits); this will continue until the st bit is reset by soft- ware. in all cases, an ecv interrupt is issued each time channel 7 conversion ends. when channel 'i' is converted ('s' <'i' <7), the relat- ed data register is reloaded with the new conver- sion result and the previous value is lost. the end of conversion (ecv) interrupt service routine can be used to save the current values before a new conversion sequence (so as to create signal sam- ple tables in the register file or in memory). 7.6.2.2 triggering and synchronisation in both modes, conversion may be triggered by in- ternal or external conditions; externally this may be tied to extrg, as an alternate function input on an i/o port pin, and internally, it may be tied to intrg, generated by a multifunction timer pe- ripheral. both external and internal events can be separately masked by programming the extg/ intg bits of the control logic register (clr). the events are internally ored, thus avoiding potential hardware conflicts. however, the correct proce- dure is to enable only one alternate synchronisa- tion condition at any time. the effect either of these synchronisation modes is to set the st bit by hardware. this bit is reset, in single mode only, at the end of each group of con- versions. in continuous mode, all trigger pulses after the first are ignored. the synchronisation sources must be at a logic low level for at least the duration of one intclk cycle and, in single mode, the period between trig- ger pulses must be greater than the total time re- quired for a group of conversions. if a trigger oc- curs when the st bit is still set, i.e. when conver- sion is still in progress, it will be ignored. 9
149/179 st92141 - analog to digital converter (adc) analog to digital converter (contd) on devices where two a/d converters are present they can be triggered from the same source. 7.6.2.3 analog watchdogs two internal analog watchdogs are available for highly flexible automatic threshold monitoring of external analog signal levels. analog channels 6 and 7 monitor an acceptable voltage level window for the converted analog in- puts. the external voltages applied to inputs 6 and 7 are considered normal while they remain below their respective upper thresholds, and above or at their respective lower thresholds. when the external signal voltage level is greater than, or equal to, the upper programmed voltage limit, or when it is less than the lower programmed voltage limit, a maskable interrupt request is gen- erated and the compare results register is up- dated in order to flag the threshold (upper or low- er) and channel (6 or 7) responsible for the inter- rupt. the four threshold voltages are user pro- grammable in dedicated registers (08h to 0bh) of the adc register page. only the 4 msbs of the compare results register are used as flags, each of the four msbs being associated with a threshold condition. following a reset, these flags are reset. during normal adc operation, the crr bits are set, in or- der to flag an out of range condition and are auto- matically reset by hardware after a software reset of the analog watchdog request flag in the icr register. 7.6.2.4 power down mode before enabling an a/d conversion, the pow bit of the control logic register must be set; this must be done at least 60s before the first conversion start, in order to correctly bias the analog section of the converter circuitry. when the adc is not required, the pow bit may be reset in order to reduce the total power con- sumption. this is the reset configuration, and this state is also selected automatically when the st9 is placed in halt mode (following the execution of the halt instruction). figure 79. a/d trigger source converter external trigger on chip event (internal trigger) a/d 0 extrg pin mft 0 a/d 1 analog voltage upper threshold lower threshold normal area (window guarded) 9
150/179 st92141 - analog to d igital converter (adc) analog to digital converter (contd) figure 80. application example: analog watchdog used in motorspeed control 7.6.3 interrupts the adc provides two interrupt sources: C end of conversion C analog watchdog request the a/d interrupt vector register (ivr) provides hardware generated flags which indicate the inter- rupt source, thus allowing automatic selection of the correct interrupt service routine. the a/d interrupt vector should be programmed by the user to point to the first memory location in the interrupt vector table containing the base ad- dress of the four byte area of the interrupt vector table in which the address of the a/d interrupt service routines are stored. the analog watchdog interrupt pending bit (awd, icr.6), is automatically set by hardware whenever any of the two guarded analog inputs go out of range. the compare result register (crr) tracks the analog inputs which exceed their programmed thresholds. when two requests occur simultaneously, the an- alog watchdog request has priority over the end of conversion request, which is held pending. the analog watchdog request requires the user to poll the compare result register (crr) to de- termine which of the four thresholds has been ex- ceeded. the threshold status bits are set to flag an out of range condition, and are automatically reset by hardware after a software reset of the analog watchdog request flag in the icr register. the interrupt pending flags, ecv and awd, should be reset by the user within the interrupt service rou- tine. setting either of these two bits by software will cause an interrupt request to be generated. analog watch- dog re- quest 70 lower word address xxxxxx0 0 end of conv. request 70 upper word address xxxxxx1 0 9
151/179 st92141 - analog to digital converter (adc) 7.6.4 register description data registers (dir) the conversion results for the 8 available chan- nels are loaded into the 8 data registers following conversion of the corresponding analog input. channel 0 data register (d0r) r240 - read/write register page: 63 reset value: undefined bit 7:0 = d0.[7:0]: channel 0 data channel 1 data register (d1r) r241 - read/write register page: 63 reset value: undefined bit 7:0 = d1.[7:0]: channel 1 data channel 2 data register (d2r) r242 - read/write register page: 63 reset value: undefined bit 7:0 = d2.[7:0]: channel 2 data channel 3 data register (d3r) r243 - read/write register page: 63 reset value: undefined bit 7:0 = d3.[7:0]: channel 3 data channel 4 data register (d4r) r244 - read/write register page: 63 reset value: undefined bit 7:0 = d4.[7:0]: channel 4 data channel 5 data register (d5r) r245 - read/write register page: 63 reset value: undefined bit 7:0 = d5.[7:0]: channel 5 data channel 6 data register (d6r) r246 - read/write register page: 63 reset value: undefined bit 7:0 = d6.[7:0]: channel 6 data channel 7 data register (d7r) r247 - read/write register page: 63 reset value: undefined bit 7:0 = d7.[7:0]: channel 7 data 70 d0.7 d0.6 d0.5 d0.4 d0.3 d0.2 d0.1 d0.0 70 d1.7 d1.6 d1.5 d1.4 d1.3 d1.2 d1.1 d1.0 70 d2.7 d2.6 d2.5 d2.4 d2.3 d2.2 d2.1 d2.0 70 d3.7 d3.6 d3.5 d3.4 d3.3 d3.2 d3.1 d3.0 70 d4.7 d4.6 d4.5 d4.4 d4.3 d4.2 d4.1 d4.0 70 d5.7 d5.6 d5.5 d5.4 d5.3 d5.2 d5.1 d5.0 70 d6.7 d6.6 d6.5 d6.4 d6.3 d6.2 d6.1 d6.0 70 d7.7 d7.6 d7.5 d7.4 d7.3 d7.2 d7.1 d7.0 9
152/179 st92141 - analog to d igital converter (adc) register description (contd) lower threshold registers (ltir) the two lower threshold registers are used to store the user programmable lower threshold 8-bit values, to be compared with the current conver- sion results, thus setting the lower window limit. channel 6 lower threshold register (lt6r) r248 - read/write register page: 63 reset value: undefined bit 7:0 = lt6.[7:0]: channel 6 lower threshold channel 7 lower threshold register (lt7r) r249 - read/write register page: 63 reset value: undefined bit 7:0 = lt7.[7:0] : channel 7 lower threshold upper threshold registers (utir) the two upper threshold registers are used to store the user programmable upper threshold 8-bit values, to be compared with the current conver- sion results, thus setting the upper window limit. channel 6 upper threshold register (ut6r) r250 - read/write register page: 63 reset value: undefined bit 7:0 = ut6.[7:0] : channel 6 upper threshold value channel 7 upper threshold register (ut7r) r251 - read/write register page: 63 reset value: undefined bit 7:0 = ut7.[7:0] : channel 7 upper threshold value 70 lt6.7 lt6.6 lt6.5 lt6.4 lt6.3 lt6.2 lt6.1 lt6.0 70 lt7.7 lt6.7 lt7.5 lt7.4 lt7.3 lt7.2 lt7.1 lt7.0 70 ut6.7 ut6.6 ut6.5 ut6.4 ut6.3 ut6.2 ut6.1 ut6.0 70 ut7.7 ut6.7 ut7.5 ut7.4 ut7.3 ut7.2 ut7.1 ut7.0 9
153/179 st92141 - analog to digital converter (adc) register description (contd) compare result register (crr) r252 - read/write register page: 63 reset value: 0000 1111 (0fh) the result of the comparison between the current value of data registers 6 and 7 and the threshold registers is stored in the 4 most significant bits of this register. bit 7 = c7u : compare reg 7 upper threshold set when converted data is greater than or equal to the threshold value. not affected otherwise. bit 6 = c6u : compare reg 6 upper threshold set when converted data is greater than or equal to the threshold value. not affected otherwise. bit 5 = c7l : compare reg 7 lower threshold set when converted data is less than the threshold value. not affected otherwise. bit 4 = c6l : compare reg 6 lower threshold set when converted data is less than the threshold value. not affected otherwise. these bits should be reset at the end of the out of range interrupt service routine. note : any software reset request of the icr, will also cause all the compare status bits to forced by hardware to zero, in order to prevent possible overwriting if an interrupt request occurs between reset and the interrupt request software reset. bit 3 = undefined, return '1' when red. bit 2:0 = pr[2:0] : clock divider bits these bits enable a frequency division factor de- pending on the value stored: table 30. frequency division factors warning: if the prescaler programming value is changed during a conversion, the user has to re- start the conversion (i.e. simply rewriting the clr register with the same value). 70 c7u c6u c7l c6l x pr2 pr1 pr0 pr[2:0] bits freq. div. factor (fdf) max. con- version time (intclk) min. sam- pling time (intclk) 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 4 6 8 10 12 14 16 138 552 828 1104 1380 1656 1932 2208 84 336 504 672 840 1008 1176 1344 9
154/179 st92141 - analog to d igital converter (adc) register description (contd) control logic register (clr) the control logic register (clr) manages the adcs logic. writing to this register will cause the current conversion to be aborted and the autoscan logic to be re-initialized. clr is programmable as follows: control logic register (clr) r253 - read/write register page: 63 reset value: 0000 0000 (00h) bit 7:5 = sc[2:0]: start conversion address . these 3 bits define the starting analog input chan- nel (autoscan mode). the first channel addressed by sc[2:0] is converted, then the channel number is incremented for the successive conversion, until channel 7 (111) is converted. when sc2, sc1 and sc0 are all set, only channel 7 will be converted. bit 4 = extg : external trigger enable . this bit is set and cleared by software. 0: external trigger disabled. 1: external trigger enabled. allows a conversion sequence to be started on the subsequent edge of the external signal applied to the extrg pin (when enabled as an alternate function). bit 3 = intg : internal trigger enable . this bit is set and cleared by software. 0: internal trigger disabled. 1: internal trigger enabled. allows a conversion se- quence to be started, synchronized by an inter- nal signal (on-chip event signal) from a multi- function timer peripheral. both external and internal trigger inputs are inter- nally ored, thus avoiding hardware conflicts; however, the correct procedure is to enable only one alternate synchronization input at a time. note: the effect of either synchronization mode is to set the start/stop bit, which is reset by hard- ware when in single mode, at the end of each sequence of conversions. requirements: the external synchronisation in- put must receive a low level pulse wider than an intclk period and, for both external and on-chip event synchronisation, the repetition period must be greater than the time required for the selected sequence of conversions. bit 2 = pow : power up/power down. this bit is set and cleared by software. 0: power down mode: all power-consuming logic is disabled, thus selecting a low power idle mode. 1: power up mode: the a/d converter logic and an- alog circuitry is enabled. bit 1 = cont : continuous/single . 0: single mode: a single sequence of conversions is initiated whenever an external (or internal) trigger occurs, or when the st bit is set by soft- ware. 1: continuous mode: the first sequence of conver- sions is started, either by software (by setting the st bit), or by hardware (on an internal or ex- ternal trigger, depending on the setting of the intg and extg bits); a continuous conversion sequence is then initiated. bit 0 = st : start/stop. 0: stop conversion. when the a/d converter is running in single mode, this bit is hardware re- set at the end of a sequence of conversions. 1: start a sequence of conversions. 70 sc2 sc1 sc0 extg intg pow cont st 9
155/179 st92141 - analog to digital converter (adc) register description (contd) interrupt control register (ad_icr) the interrupt control register contains the three priority level bits, the two source flags, and their bit mask: interrupt control register (ad_icr) r254 - read/write register page: 63 reset value: 0000 1111 (0fh) bit 7 = ecv : end of conversion. this bit is automatically set by hardware after a group of conversions is completed. it must be re- set by the user, before returning from the interrupt service routine. setting this bit by software will cause a software interrupt request to be generat- ed. 0: no end of conversion event occurred 1: an end of conversion event occurred bit 6 = awd : analog watchdog. this is automatically set by hardware whenever ei- ther of the two monitored analog inputs goes out of bounds. the threshold values are stored in regis- ters f8h and fah for channel 6, and in registers f9h and fbh for channel 7 respectively. the com- pare result register (crr) keeps track of the an- alog inputs exceeding the thresholds. the awd bit must be reset by the user, before re- turning from the interrupt service routine. setting this bit by software will cause a software interrupt request to be generated. 0: no analog watchdog event occurred 1: an analog watchdog event occurred bit 5 = eci : end of conversion interrupt enable. this bit masks the end of conversion interrupt re- quest. 0: mask end of conversion interrupts 1: enable end of conversion interrupts bit 4 = awdi : analog watchdog interrupt enable . this bit masks or enables the analog watchdog interrupt request. 0: mask analog watchdog interrupts 1: enable analog watchdog interrupts bit 3 = reserved. bit 2:0 = pl[2:0]: a/d interrupt priority level . these three bits allow selection of the interrupt pri- ority level for the adc. interrupt vector register (ad_ivr) r255 - read/write register page: 63 reset value: xxxx xx10 (x2h ) bit 7:2 = v[7:2]: a/d interrupt vector. this vector should be programmed by the user to point to the first memory location in the interrupt vector table containing the starting addresses of the a/d interrupt service routines. bit 1 = w1 : word select. this bit is set and cleared by hardware, according to the a/d interrupt source. 0: interrupt source is the analog watchdog, point- ing to the lower word of the a/d interrupt service block (defined by v[7:2]). 1:interrupt source is the end of conversion inter- rupt, thus pointing to the upper word. note: when two requests occur simultaneously, the analog watchdog request has priority over the end of conversion request, which is held pending. bit 0 = reserved. forced by hardware to 0. 70 ecv awd eci awdi x pl2 pl1 pl0 70 v7 v6 v5 v4 v3 v2 w1 0 9
156/179 st92141 - electrical characteristics 8 electrical characteristics this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precautions to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v in and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations . the average chip-junc- tion temperature, t j , in celsius can be obtained from: t j =t a + p d x rthja where: t a = ambient temperature. rthja = package thermal resistance (junction-to ambient). p d = p int + p port . p int =i dd x v dd (chip internal power). p port = port power dissipation (determined by the user) absolute maximum ratings note : stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating onl y and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended perio ds may affect device reliability. all voltages are referenced to v ss =0. (1) av dd can be shut down while the a/d converter is not in use. thermal characteristics recommended operating conditions note : (1) device is reset whenever supply voltage is below lvd thresholds (2) 1mhz when a/d is used with its internal prescaler programmed to 1. symbol parameter value unit v dd supply voltage C 0.3 to 6.5 v av dd a/d converter analog reference up to v dd + 0.3 (1) v av ss a/d converter v ss v ss v in input voltage (standard i/o pins) C 0.3 to v dd + 0.3 v v ain analog input voltage (a/d converter) av ss to av dd v esd esd susceptibility 2000 v t stg storage temperature C 55 to +150 c i inj pin injection current - digital and analog input +/- 10 ma maximum accumulated pin injection current +/- 100 ma symbol package value unit rthja pdip32sh pso34sh 60 75 c/w symbol parameter value unit min max t a operating temperature C40 85 c v dd operating supply voltage (1) 4.5 5.5 v av dd analog supply voltage 0 v dd + 0.3 v f intclk internal clock frequency @ 4.5v - 5.5v 0 (2) 25 mhz 1
157/179 st92141 - electrical characteristics dc electrical characteristics (v dd = 5v 10%, t a = C 40c to +85c, unless otherwise specified) note: (1) unless otherwise stated, typical data are based on t a =25 c and v dd =5v. they are only reported for design guidelines - not tested in pro- duction. (2) data based on characterization results - not tested in production. (3) for a description of the emr1 register - bsz bit refer to the device configuration registers chapter. symbol parameter comment value unit min typ (1) max v ih input high level standard schmitt trigger p5[7:2] 0.7v dd v dd + 0.3 v input high level high hyst. schmitt trigger p5[1:0]-p3[6:0]-tacho 0.8v dd v dd + 0.3 v v il input low level standard schmitt trigger p5[7:2] C 0.3 0.8 v input low level high hyst. schmitt trigger p5[1:0]-p3[6:0]-tacho C 0.3 0.8 v v hys input hysteresis (2) standard schmitt trigger p5[7:2] 0.5 v input hysteresis (2) high hyst. schmitt trigger p5[1:0]-p3[6:0]-tacho 1.5 v v oh output high level high current pins p3.5-p3.6-p5.0-p5.2 push pull, i oh = C 2ma emr1 register - bsz bit = 0 (3) v dd C 0.8 v psh pull, i oh = C 8ma emr1 register - bsz bit = 1 (3) v dd C 0.8 v output high level standard current pins p3[4:0]-p3.7-p5.1-p5[7:3]- uh-ul-vh-vl-wh-wl push pull, i oh = C 2ma v dd C 0.8 v v ol output low level high current pins p3.5-p3.6-p5.0-p5.2 push pull, i ol =2ma emr1 regis- ter - bsz bit = 0 (3) 0.4 v push pull, i ol =8ma, emr1 reg- ister - bsz bit = 1 (3) 0.4 v push pull, i ol =20ma, emr1 reg- ister - bsz bit = 1 (3) 3v output low level standard current pins p3[4:0]-p3.7-p5.1-p5[7:3]- uh-ul-vh-vl-wh-wl push pull, i ol =2ma 0.4 v i wpu weak pull-up current p5[7:0]-p3[6:0] bidirectional weak pull-up v ol = 0v 50 600 m a i lkio i/o pin input leakage input/tri-state, 0v < v in < v dd C 10 + 10 m a i lka/d a/d conv. input leakage C 1 + 1 m a 1
158/179 st92141 - electrical characteristics low voltage detector dc characteristics (v dd = 5v 10%, t a = C 40c to +85c, unless otherwise specified) note: (1) unless otherwise stated, typical data are based on t a =25 c and v dd =5v. they are only reported for design guidelines - not tested in pro- duction. (2) data based on characterization results - not tested in production symbol parameter test conditions min typ (1) max unit v lvdr reset release threshold v dd rise - halt mode 4.2 v v lvdf reset generation threshold v dd fall - halt mode 3.4 v v lvdhyst hysteresis (2) halt mode 200 mv i ddlvd supply current halt mode 250 m a 1
159/179 st92141 - electrical characteristics ac electrical characteristics (v dd = 5v 10%, t a = C 40c to +85c, unless otherwise specified) note: all i/o ports are configured to a static value of vdd or vss, external clock pin (oscin) is driven by square wave external cloc k. (1) unless otherwise stated, typical data are based on t a =25 c and v dd =5v. they are only reported for design guidelines - not tested in production. (2) cpu running with memory access, all peripherals switched off. symbol parameter intclk typ (1) max unit i ddrun run mode current (2) 25 mhz 50 ma i ddwfi wfi mode current 25 mhz 15 ma i ddlpwfi low power wfi mode current 125 khz 2 ma i ddhalt halt mode current - 250 m a 1
160/179 st92141 - electrical characteristics external interrupt timing table (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period. the value in the right hand two columns show the timing minimum and maximum for an internal clock at 25mhz (intclk). measurement points are taken with reference to v ih -v ih for positive pulse and v il -v il for negative pulse (1) formula guaranteed by design. legend : tck = intclk period = oscin period when oscin is not divided by 2; 2 x oscin period when oscin is divided by 2; oscin period x pll factor when the pll is enabled. external interrupt timing n symbol parameter value (note) unit formula (1) min max 1 twintlr low level pulse width in rising edge mode 3 tck+10 50 ns 2 twinthr high level pulse width in rising edge mode 3 tck+10 50 ns 3 twinthf high level pulse width in falling edge mode 3 tck+10 50 ns 4 twintlf low level pulse width in falling edge mode 3 tck+10 50 ns n=0,6 1
161/179 st92141 - electrical characteristics wake-up management timing table (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period. the value in the right hand two columns show the timing minimum and maximum for an internal clock at 25mhz (intclk). the given data are related to wake-up management unit used in external interrupt mode. measurement points are taken with reference to v ih -v ih for positive pulse and v il -v il for negative pulse (1) formula guaranteed by design. legend : tck = intclk period = oscin period when oscin is not divided by 2; 2 x oscin period when oscin is divided by 2; oscin period x pll factor when the pll is enabled. wake-up management timing n symbol parameter value (note) unit formula (1) min max 1 twwkplr low level pulse width in rising edge mode 3 tck+10 50 ns 2 twwkphr high level pulse width in rising edge mode 3 tck+10 50 ns 3 twwkphf high level pulse width in falling edge mode 3 tck+10 50 ns 4 twwkplf low level pulse width in falling edge mode 3 tck+10 50 ns wkupn n=0-3 1
162/179 st92141 - electrical characteristics rccu characteristics (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note : (1) unless otherwise stated, typical data are based on t a =25 c and v dd =5v. they are only reported for design guidelines - not tested in pro- duction. (2) data based on characterization results - not tested in production rccu timing table (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note: (1) depending on the delay between rising edge of reset pin and the first rising edge of clock1, the value can differ from the typical value for +/- 1 clock1 cycle. legend : t osc = oscin period pll characteristics (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note: (1) measured with pll output clock frequency equal to 25mhz. data based on characterization results - not tested in production. legend : tosc = oscin period symbol parameter comment value (note) unit min typ (1) max v ihrs reset input high level 0.7v dd v dd + 0.3 v v ilrs reset input low level C 0.3 0.3v dd v v hyrs reset input hysteresis (2) 900 mv i lkrs reset pin input leakage 0v < v in < v dd C 10 + 10 m a symbol parameter comment value (note) unit min typ max t frs reset input filtered pulse 50 ns t nfrs reset input not filtered pulse 20 m s t rsph (1) reset phase duration 20478 x t osc m s t str stop restart duration div2 = 0 div2 = 1 10239 x t osc 20478 x t osc m s symbol parameter comment value (note) unit min typ max f vco vco operating frequency 6 25 mhz t plk lock-in time 1000 x tosc m s pll jitter 0 1.2 (1) ns 1
163/179 st92141 - electrical characteristics oscillator characteristics (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note : (1) unless otherwise stated, typical data are based on t a =25 c and v dd =5v. they are only reported for design guidelines - not tested in pro- duction. (2) typical value with oscin=5mhz, cl=33pf on oscin-oscout, t a =25 c, v dd =5v. the value depends on resonator quality as well. symbol parameter comment value (note) unit min typ (1) max f osc crystal frequency fundamental mode crystal only 3 5 mhz g m oscillator 0.6 1.4 2.5 ma/v v ihck clock input high level external clock 0.8v dd v dd + 0.3 v v ilck clock input low level external clock C 0.3 0.2v dd v i lkos oscin/oscout pins input leakage 0v < v in < v dd (halt/stop) C 10 + 10 m a t stup oscillator start-up time 6 (2) ms 1
164/179 st92141 - electrical characteristics watchdog timing table (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, push-pull output configuration, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, watchdog prescaler and counter programmed values. the value in the right hand two columns show the timing minimum and maximum for an internal clock (intclk) at 25mhz, with minim um and maximum prescaler value and minimum and maximum counter value. measurement points are taken with reference to v ih -v ih / v oh -v oh for positive pulse and v il -v il / v ol -v ol for negative pulse (1) formula guaranteed by design. legend : tck = intclk period = oscin period when oscin is not divided by 2; 2 x oscin period when oscin is divided by 2; oscin period x pll factor when the pll is enabled. psc = watchdog prescaler register content (wdtpr): from 0 to 255 cnt = watchdog counter registers content (wdtrh,wdtrl): from 0 to 65535 t wdin = watchdog input signal period (wdin) watchdog timing n symbol parameter value (note) unit formula (1) min max 1 twwdol wdout low pulse width 4 x (psc+1) x (cnt+1) x tck 160 2.69 ns s (psc+1) x (cnt+1) x t wdin with t wdin 3 8 x tck 320 ns 2 twwdoh wdout high pulse width 4 x (psc+1) x (cnt+1) x tck 160 2.69 ns s (psc+1) x (cnt+1) x t wdin with t wdin 3 8 x tck 320 ns 3 twwdil wdin high pulse width 3 4 x tck + 10 170 ns 4 twwdih wdin low pulse width 3 4 x tck +10 170 ns 1
165/179 st92141 - electrical characteristics standard timer timing table (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, push-pull output configuration, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. the value in the right hand two columns show the timing minimum and maximum for an internal clock (intclk) at 25mhz, with minim um and maximum prescaler value and minimum and maximum counter value. measurement points are taken with reference to v ih -v ih / v oh -v oh for positive pulse and v il -v il / v ol -v ol for negative pulse (1) formula guaranteed by design. legend : tck = intclk period = oscin period when oscin is not divided by 2; 2 x oscin period when oscin is divided by 2; oscin period x pll factor when the pll is enabled. psc = standard timer prescaler register content (stp): from 0 to 255 cnt = standard timer counter registers content (sth,stl): from 0 to 65535 t stin = standard timer input signal period (stin). standard timer timing n symbol parameter value (note) unit formula (1) min max 1 twstol stout low pulse width 4 x (psc+1) x (cnt+1) x tck 160 2.69 ns s (psc+1) x (cnt+1) x t stin with t stin 3 8 x tck 320 ns 2 twstoh stout high pulse width 4 x (psc+1) x (cnt+1) x tck 160 2.69 ns s (psc+1) x (cnt+1) x t stin with t stin 3 8 x tck 320 ns 3 twstil stin high pulse width 3 4 x tck + 10 170 ns 4 twstih stin low pulse width 3 4 x tck + 10 170 ns 1
166/179 st92141 - electrical characteristics extended function timer external timing table (v dd = 5v 10%, t a = C 40c to +105c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. the value in the right hand two columns show the timing minimum and maximum for an internal clock (intclk) at 25mhz, and minimu m prescaler factor (=2). measurement points are taken with reference to v ih -v ih for positive pulse and v il -v il for negative pulse (1) formula guaranteed by design. legend : tck = intclk period = oscin period when oscin is not divided by 2; 2 x oscin period when oscin is divided by 2; oscin period x pll factor when the pll is enabled. prsc = prescaler factor defined by extended function timer clock control bits (cc1,cc0) on control register cr2 (values: 2,4,8) . extended function timer external timing n symbol parameter value unit formula (1) min 1tw pewl external clock low pulse width (extclk) 2 x tck + 10 90 ns 2tw pewh external clock high pulse width (extclk) 2 x tck + 10 90 ns 3tw piwl input capture low pulse width (icapx) 2 x tck + 10 90 ns 4tw piwh input capture high pulse width (icapx) 2 x tck + 10 90 ns 5tw eckd distance between two active edges on extclk 3 4 x tck + 10 170 ns 6tw eicd distance between two active edges on icapx 2 x tck x prsc +10 170 ns 1 2 5 extclk 34 6 icapa icapb 1
167/179 st92141 - electrical characteristics spi timing table (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note: measurement points are taken with reference to v ih -v ih / v oh -v oh for positive pulse and v il -v il / v ol -v ol for negative pulse (1) values guaranteed by design. legend : tck = intclk period = oscin period when oscin is not divided by 2; 2 x oscin period when oscin is divided by 2; oscin period x pll factor when the pll is enabled. n symbol parameter condition value (1) unit min max f spi spi frequency master slave f intclk / 128 0 f intclk / 4 f intclk / 2 mhz 1t spi spi clock period master slave 4 x tck 2 x tck ns 2t lead enable lead time slave 40 ns 3t lag enable lag time slave 40 ns 4t spi_h clock (sck) high time master slave 80 90 ns 5t spi_l clock (sck) low time master slave 80 90 ns 6t su data set-up time master slave 40 40 ns 7t h data hold time (inputs) master slave 40 40 ns 8t a access time (time to data active from high impedance state) slave 0 120 ns 9t dis disable time (hold time to high im- pedance state) 240 ns 10 t v data valid master (before capture edge) slave (after enable edge) tck / 4 120 ns ns 11 t hold data hold time (outputs) master (before capture edge) slave (after enable edge) tck / 4 0 ns ns 12 t rise rise time (20% v dd to 70% v dd , c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 13 t fall fall time (70% v dd to 20% v dd , c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 1
168/179 st92141 - electrical characteristics spi master timing diagram cpha=0, cpol=0 spi master timing diagram cpha=0, cpol=1 spi master timing diagram cpha=1, cpol=0 spi master timing diagram cpha=1, cpol=1 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 45 d7-out d6-out d0-out d7-in d6-in d0-in vr000109 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000110 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 5 4 vr000107 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000108 d7-out d6-out d0-out d7-in d6-in d0-in 1
169/179 st92141 - electrical characteristics spi slave timing diagram cpha=0, cpol=0 spi slave timing diagram cpha=0, cpol=1 spi slave timing diagram cpha=1, cpol=0 spi slave timing diagram cpha=1, cpol=1 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000113 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000114 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000111 d7-out d6-out d0-out d7-in d6-in d0-in 1 67 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z d7-out d6-out d0-out d7-in d6-in d0-in vr000112 1
170/179 st92141 - electrical characteristics a/d external trigger timing table (v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. the value in the right hand two columns show the timing minimum and maximum for an internal clock (intclk) at 25mhz. measurement points are taken with reference to v ih -v ih for positive pulse and v il -v il for negative pulse (1) formula guaranteed by design. legend : tck = intclk period = oscin period when oscin is not divided by 2; 2*oscin period when oscin is divided by 2; oscin period / pll factor when the pll is enabled. n = number of autoscanned channels (1 n 8) fdf = frequency division factor (adc prescaler factor), refer to section 7.6.1 on page 147 a/d external trigger timing n symbol parameter value (note) unit formula (1) min. max. 1tw low external trigger pulse width 3 1.5 x tck 60 - ns 2tw high external trigger pulse distance 3 1.5 x tck 60 - ns 3tw ext external trigger active edges distance 3 138 x n x fdf x tck n x fdf x 5.52 - m s 4td str extrg falling edge and first conversion start 0.5 x tck 1.5 x tck 20 60 ns 1
171/179 st92141 - electrical characteristics a/d analog specifications (v dd = 5v, t a = 2 5c, f intclk = 25mhz, unless otherwise specified) note : (1) 1lsbideal has a value of av dd /256 (2) including sample time (3) this is the internal series resistance before the sampling capacitor (4) this is a typical expected value, but not a tested production parameter. if v(i) is the value of the i-th transition level (0 i 254), the performance of the a/d converter has been evaluated as follows: offset error= deviation between the actual v(0) and the ideal v(0) (=1/2 lsb) gain error= deviation between the actual v(254) and the ideal v(254) - v(0) (ideal v(254)=av dd -3/2 lsb) dnl error= max {[v(i) - v(i-1)]/lsb - 1} inl error= max {[v(i) - v(0)]/lsb - i} abs. accuracy= overall max conversion error (5) simulated value. (6) the specified values are guaranteed only if an overload condition occurs on a maximum of 2 non-selected analog input pins an d the absolute sum of input overload currents on all analog input pins does not exceed 10 ma. parameter typical minimum maximum units (1) notes conversion time 138 intclk (2)(6) sample time 85 intclk (6) power-up time 60 m s (6) resolution 8 8 bits monotonicity guaranteed no missing codes guaranteed zero input reading 00 hex (6) full scale reading ff hex (6) offset error 1 lsbs (1)(4)(6) gain error 1 lsbs (4)(6) diff. non linearity error (dnl) 1 lsbs (4)(6) int. non linearity error (inl) 1 lsbs (4)(6) absolute accuracy 2 lsbs (4)(6) input resistance 2.7 k w (3)(5)(6) hold capacitance 1.4 pf (5)(6) input leakage 1 m a (6) 1
172/179 st92141 - electrical characteristics figure 81. a/d conversion characteristics (2) (1) (3 ) (4) (5) vr02133a offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 255 254 253 252 251 250 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 250 251 252 253 254 255 256 1
173/179 st92141 - electrical characteristics imc timing table v dd = 5v 10%, t a = C 40c to +85c, c load = 50pf, f intclk = 25mhz, unless otherwise specified) note : the value in the left hand column shows the formula used to calculate the minimum or maximum timing from the oscillator clock period. the value in the right hand two columns show the minimum and maximum timing for an internal clock at 25mhz (intclk). measurement points are taken with reference to v ih -v ih for positive pulse and v il -v il for negative pulse (1) formula guaranteed by design. legend : tck = intclk period = oscin period when oscin is not divided by 2; 2 x oscin period when oscin is divided by 2; oscin period x pll factor when the pll is enabled. imc timing n symbol parameter value (note) unit formula (1) min max 1 twtaclr tacho low level minimum pulse width in rising edge mode tck 40 ns 2 twtachr tacho high level minimum pulse width in ris- ing edge mode tck 40 ns 3 twtachf tacho high level minimum pulse width in fall- ing edge mode tck 40 ns 4 twtaclf tacho low level minimum pulse width in fall- ing edge mode tck 40 ns 5 twnmilr nmi low level minimum pulse width in rising edge mode 1000 ns 6 twnmihr nmi high level minimum pulse width in rising edge mode 1000 ns 7 twnmihf nmi high level minimum pulse width in falling edge mode 1000 ns 8 twnmilf nmi low level minimum pulse width in falling edge mode 1000 ns 9 tdphz delay from nmi to phases in high impedance 1000 ns 5 6 7 8 / 9 tacho nmi nmi uh/ul/vh/vl/wh/wl 1
174/179 st92141 - general information 9 general information 9.1 package mechanical data 32-pin shrink plastic dual in line package 34-pin plastic small outline package dim. mm inches min typ max min typ max a 3.56 3.76 5.08 0.140 0.148 0.200 a1 0.51 0.020 a2 3.05 3.56 4.57 0.120 0.140 0.180 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.76 1.02 1.40 0.030 0.040 0.055 c 0.20 0.25 0.36 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.91 10.41 11.05 0.390 0.410 0.435 e1 7.62 8.89 9.40 0.300 0.350 0.370 e 1.78 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.54 3.05 3.81 0.100 0.120 0.150 number of pins n32 1 n b d vr01725j n/2 b1 e a l see lead detail e 1 e 3 a 2 a 1 e c e b e a dim. mm inches min typ max min typ max a 2.46 2.64 0.097 0.104 a1 0.13 0.29 0.005 0.0115 b 0.36 0.48 0.014 0.019 c 0.23 0.32 0.0091 0.0125 d 17.73 18.06 0.698 0.711 e 7.42 7.59 0.292 0.299 e 1.02 0.040 h 10.16 10.41 0.400 0.410 h 0.64 0.74 0.025 0.029 k 0 8 l 0.61 1.02 0.024 0.040 number of pins n34 so34s 0.10mm .004 seating plane 1
175/179 st92141 - general information 32-pin shrink ceramic dual in-line package dim. mm inches min typ max min typ max a 3.63 0.143 a1 0.38 0.015 b 0.36 0.46 0.58 0.014 0.018 0.023 b1 0.64 0.89 1.14 0.025 0.035 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 d 29.41 29.97 30.53 1.158 1.180 1.202 d1 26.67 1.050 e 10.16 0.400 e1 9.45 9.91 10.36 0.372 0.390 0.408 e 1.78 0.070 g 9.40 0.370 g1 14.73 0.580 g2 1.12 0.044 l 3.30 0.130 ? 7.37 0.290 number of pins n32 cdip32sw 1
176/179 st92141 - general information 9.2 ordering information the following section deals with the procedure for transfer of customer codes to stmicroelectronics. 9.3 transfer of customer code customer code is made up of the fastrom ( factory advanced service technique rom) con- tents. the fastrom contents are to be sent on diskette, or by electronic means, with the hexadec- imal file generated by the development tool. all un- used bytes must be set to ffh. the customer code should be communicated to stmicroelectronics with the correctly completed option list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 82. sales type coding rules table 31. ordering information note 1: xxx stands for the fastrom code name assigned by stmicroelectronics. table 32. development tools st92 t 141 k 4 b 6 / xxx family version code subfamily number of pins rom size package temperature range fastrom code (three letters) 0 = 25c b = plastic dip 4 = 16k k= 32/34 pins p = fastrom 6 = industrial (-40 to +85c) d = ceramic dip 0 = special e = eprom m = plastic sop t = otp sales type 1) program memory (bytes) ram (bytes) package st92p141k4b6/xxx 16k fastrom 512 psdip32 st92p141k4m6/xxx so34 st92e141k4d0 16k eprom 512 csdip32w ST92T141K4B6 16k otp 512 psdip32 st92t141k4m6 so34 development tool sales type remarks real time emulator st92141-emu2 eprom programming board st92e141-epb/eu st92e141-epb/us 220v power supply 110v power supply gang programmer third party product available from leap at www.leap.com.tw sdip32 package so34 package c hiware compiler and debugger st9p-swc/pc for pc 1
177/179 st92141 - general information stmicroelectronics option list st92p141 microcontroller family (fastrom device) customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/fastrom code* :. . . . . . . . . . . . . . *the fastrom code name is assigned by stmicroelectronics. stmicroelectronics reference: device (psdip32): [ ] st92p141k4b6/xxx* device (so34): [ ] st92p141k4m6/xxx* conditioning: [ ] tube [ ] tape & reel (not available for sdip packages) *xxx = fastrom code name software development: [ ] stmicroelectronics [ ] customer [ ] external laboratory special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" for marking, one line is possible with maximum 10 characters for psdip32 and 16 characters for so34. authorized characters are letters, digits, '.', '-', '/' and spaces only. we have checked the fastrom code verification file returned to us by stmicroelectronics. it con- forms exactly with the fastrom code file orginally supplied. we therefore authorize stmicroelec- tronics to proceed with device manufacture. signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
178/179 st92141 - summary of changes 10 summary of changes description of the changes between the current release of the specification and the previous one. rev. main changes date 1.7 added paragraph in section pll clock multiplier programming on page 66 about mandatory use of the divide-by-two prescaler for pll operation. updated option list oct 01 1
179/179 st92141 - summary of changes notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 1

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